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features ? high-performance, low-power 8/16-bit atmel ? avr ? xmega tm microcontroller ? non-volatile program and data memories ? 64 kb - 256 kb of in-system self-programmable flash ? 4 kb - 8 kb boot code sectio n with independent lock bits ? 2 kb - 4 kb eeprom ? 4 kb - 16 kb internal sram ? peripheral features ? four-channel dma controller with support for external requests ? eight-channel event system ? seven 16-bit timer/counters four timer/counters with 4 output compare or input capture channels three timer/counters wi th 2 output compare or input capture channels high resolution extensions on all timer/counters advanced waveform extension on one timer/counter ? seven usarts irda extension on 1 usart ? aes and des crypto engine ? two two-wire interfaces with dual address match (i 2 c and smbus compatible) ? three spi (serial peripheral interfaces) ? 16-bit real time counter with separate oscillator ? two eight-channel, 12-bit, 2 msps analog to digital converters ? one two-channel, 12-bit, 1 msps digital to analog converter ? four analog comparators wi th window compare function ? external interrupts on a ll general purpose i/o pins ? programmable watchdog timer with sepa rate on-chip ultra low power oscillator ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll ? programmable multi-level interrupt controller ? sleep modes: idle, power-down, stan dby, power-save, extended standby ? advanced programming, test and debugging interfaces jtag (ieee 1149.1 compliant) interf ace for test, debug and programming pdi (program and debug interface) fo r programming, test and debugging ? i/o and packages ? 50 programmable i/o lines ? 64-lead tqfp ? 64-pad qfn ? operating voltage ? 1.6 ? 3.6v ? speed performance ? 0 ? 12 mhz @ 1.6 ? 3.6v ? 0 ? 32 mhz @ 2.7 ? 3.6v typical applications ? industrial control ? climate control ? hand-held battery applications ? factory automation ? zigbee ? power tools ? building control ? motor control ? hvac ? board control ? networking ? metering ? white goods ? optical ? medical applications 8/16-bit xmega a3 microcontroller atxmega256a3 atxmega192a3 ATXMEGA128A3 atxmega64a3 8068t?avr?12/10
2 8068t?avr?12/10 xmega a3 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restriction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?packaging information? on page 61 . ordering code flash e 2 sram speed (mhz) power supply package (1)(2)(3) temp atxmega256a3-au 256 kb + 8 kb 4 kb 16 kb 32 1.6 - 3.6v 64a -40 c - 85 c atxmega192a3-au 192 kb + 8 kb 2 kb 16 kb 32 1.6 - 3.6v ATXMEGA128A3-au 128 kb + 8 kb 2 kb 8 kb 32 1.6 - 3.6v atxmega64a3-au 64 kb + 4 kb 2 kb 4 kb 32 1.6 - 3.6v atxmega256a3-mh 256 kb + 8 kb 4 kb 16 kb 32 1.6 - 3.6v 64m2 atxmega192a3-mh 192 kb + 8 kb 2 kb 16 kb 32 1.6 - 3.6v ATXMEGA128A3-mh 128 kb + 8 kb 2 kb 8 kb 32 1.6 - 3.6v atxmega64a3-mh 64 kb + 4 kb 2 kb 4 kb 32 1.6 - 3.6v package type 64a 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, 7. 65 mm exposed pad, quad flat no-lead package (qfn)
3 8068t?avr?12/10 xmega a3 2. pinout/block diagram figure 2-1. block diagram and pinout. notes: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 49 . 2. the large center pad underneath the qfn/mlf package shou ld be soldered to ground on the board to ensure good mechanical stability. i n dex cor n er 17 1 8 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 50 49 4 8 47 46 45 44 43 42 41 40 39 3 8 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pf2 pf1 pf0 v cc g n d pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 v cc g n d pd7 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 g n d v cc pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 g n d v cc pd0 pd1 pd2 pd3 pd4 pd5 pd6 pa 2 pa 1 pa 0 a v cc g n d pr1 pr0 reset/pdi pdi pf7 pf6 v cc g n d pf5 pf4 pf3 flash ram e 2 prom dma interr u pt controller ocd adc a adc b dac b ac a0 ac a1 ac b0 ac b1 port a port b e v ent system ctrl port r po w er control reset control watchdog osc/clk control bod por rtc e v e n t routi n g n etwork data bu s data bu s v ref temp port c port d port e port f cpu t/c0:1 usart0:1 spi twi t/c0:1 usart0:1 spi t/c0:1 usart0:1 spi twi t/c0 usart0
4 8068t?avr?12/10 xmega a3 3. overview the atmel ? avr ? xmega ? a3 is a family of low power, high performance and peripheral rich cmos 8/16-bit microcontrollers based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the xmega a3 achieves throughputs approaching 1 million instructions per second (mips) per mhz allowing the system designer to optimize power consumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instructi on, executed in one clock cycle. the resulting architecture is more code efficient while achi eving throughputs many times faster than conven- tional single-accumula tor or cisc based microcontrollers. the xmega a3 devices provide the following features: in-system programmable flash with read- w hile- w rite capabilities, internal eeprom and sram, four-channel dma controller, eight-channel event system, programmable multi-level interrupt controller, 50 general purpose i/o lines, 16-bit real time counter (rtc), sev en flexible 16-bit timer/counters with compare modes and p w m, seven usarts, two two w ire serial interfaces (t w is), three serial periph- eral interfaces (spis), aes and des crypto engine, two 8-channel 12-bit adcs with optional differential input with programmable gain, one 2-channel 12-bit dacs, four analog comparators with window mode, programmable w atchdog timer with separate internal oscillator, accurate internal oscillators with pll and presca ler and programmable brown-out detection. the program and debug interface (pdi), a fast 2-pin interface for programming and debugging, is available. the devices also have an ieee std. 1149.1 compliant jtag test interface, and this can also be used for on-chip debug and programming. the xmega a3 devices have five software selectable power saving modes. the idle mode stops the cpu while allo wing the sram, dma controller, even t system, interrupt controller and all peripherals to continue functioning. the power-down mode saves the sram and register contents but stops the oscillators, disabling all other functions until the next t w i or pin-change interrupt, or reset. in power-save mode, the asynchronous real time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the crystal/resonator oscillator is kept running while the rest of the device is sleeping. this allows very fast start-up from external crystal combined with low power consump- tion. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in active mode and idle sleep mode. the device is manufactured using atmel's high-density nonvolatile memory technology. the pro- gram flash memory can be reprogrammed in-system through the pdi or jtag. a bootloader running in the device can use any interface to download the application program to the flash memory. the bootloader software in the boot flash section will continue to run while the appli- cation flash section is updated, providing true read- w hile- w rite operation. by combining an 8/16-bit risc cpu with in-syste m self-programmable flash, th e atmel xmega a3 is a power- ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. the xmega a3 devices are supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
5 8068t?avr?12/10 xmega a3 3.1 block diagram figure 3-1. xmega a3 block diagram pe[0..7] port e (8) tce0:1 usarte0:1 twie spie tcf0 usartf0 port f (8) power supervision por/bod & reset port a (8) port b (8) dma controller bus controller sram adca aca dacb adcb acb ocd pdi cpu pa[0..7] pb[0..7]/ jtag watchdog timer watchdog oscillator interrupt controller data bus data bus prog/debug controller vcc gnd oscillator circuits/ clock generation oscillator control real time counter event system controller jtag pdi_data reset/ pdi_clk port b sleep controller flash eeprom nvm controller des aes ircom port c (8) pc[0..7] tcc0:1 usartc0:1 twic spic pd[0..7] port r (2) xtal1 xtal2 pr[0..1] port d (8) tcd0:1 usartd0:1 spid tosc1 tosc2 event routing network pf[0..7] to clock generator int. ref. arefa arefb tempref vcc/10
6 8068t?avr?12/10 xmega a3 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4.1 recommended reading ? xmega manual ? xmega application notes this device data sheet only contains part specific information and a short description of each peripheral and module. the xmega manual describes the modules and peripherals in depth. the xmega application notes contain example code and show applied use of the modules and peripherals. the xmega manual and application notes are available from http://www.atmel.com/avr. 5. disclaimer for devices that are not available yet, typica l values contained in this datasheet are based on simulations and characterization of other av r xmega microcontrollers manufactured on the same process technology. min. and max val ues will be available after the device is characterized.
7 8068t?avr?12/10 xmega a3 6. avr cpu 6.1 features ? 8/16-bit high performan ce avr risc architecture ? 138 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16m bytes of program and data memory ? true 16/24-bit access to 16/24-bit i/o registers ? support for 8-, 16- and 32-bit arithmetic ? configuration change protection of system critical features 6.2 overview the xmega a3 uses an 8/16-bit avr cpu. the ma in function of the avr cpu is to ensure cor- rect program execution. the cpu must therefore be able to access memories, perform calculations and control peripherals. interrupt handling is described in a separate section. figure 6-1 on page 7 shows the cpu block diagram. figure 6-1. cpu block diagram the avr uses a harvard architecture - with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipeline. w hile one instruction is being executed, the next instruction is pre-fetched from the program memory. flash program memory instruction decode program counter ocd 32 x 8 general purpose registers alu multiplier/ des instruction register status/ control peripheral module 1 peripheral module 2 eeprom pmic sram data bus data bus
8 8068t?avr?12/10 xmega a3 this concept enables instructions to be executed in every clock cycle. the program memory is in-system re-programmable flash memory. 6.3 register file the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing - enabling efficient address calculations. one of these address pointers can also be used as an address pointer for look up tables in flash program memory. 6.4 alu - arithmetic logic unit the high performance arithmetic logic unit (a lu) supports arithmetic and logic operations between registers or between a constant and a regi ster. single register operations can also be executed. w ithin a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. the alu operations are divided into three main categories ? arithmetic, logical, and bit-func- tions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy implementation of 32-bit arithmetic. the alu also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format. 6.5 program flow w hen the device is powered on, the cpu starts to execute instructions from the lowest address in the flash program memory ?0?. the program counter (pc) addresses the next instruction to be fetched. after a reset, the pc is set to location ?0?. program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number uses a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sr am. after reset the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu.
9 8068t?avr?12/10 xmega a3 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and bootloader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or bootloader code ? separate lock bits and protection for all sections ? built in fast crc check of a selectable flash program memory section ? data memory ? one linear address space ? single cycle access from cpu ? sram ? eeprom byte and page accessible optional memory mapping for direct load and store ? i/o memory configuration and status register s for all peripherals and modules 16 bit-accessible general purpose regi ster for global variables or flags ? bus arbitration safe and deterministic handling of cpu and dma controller priority ? separate buses for sram, eeprom, i/o memory and external memory access simultaneous bus access for cpu and dma controller ? production signature row memory for factory programmed data device id for each microcontroller device type serial number for each device oscillator calibration bytes adc, dac and temperature sensor calibration data ? user signature row one flash page in size can be read and written from software content is kept after chip erase 7.2 overview the avr architecture has two main memory s paces, the program memory and the data mem- ory. in addition, the xm ega a3 features an eepr om memory for non-vola tile data storage. all three memory spaces are linear and require no paging. the available me mory size configura- tions are shown in ?ordering information? on page 2 . in addition each device has a flash memory signature row for calibration data, device identification, serial number etc. non-volatile memory spaces can be locked for further write or read/write operations. this pre- vents unrestricted access to the application software.
10 8068t?avr?12/10 xmega a3 7.3 in-system programmable flash program memory the xmega a3 devices contains on-chip in-system programmable flash memory for program storage, see figure 7-1 on page 10 . since all avr instructions are 16- or 32-bits wide, each flash address location is 16 bits. the program flash memory space is divided into application and boot sections. both sections have dedicated lock bits for setting restrictions on write or read/write operations. the store pro- gram memory (spm) instruction must reside in the boot section when used to write to the flash memory. a third section inside the applicat ion section is referred to as the application table section which has separate lock bits for storage of write or read/write protection. the application table sec- tion can be used for storing non-volatile data or application software. the application table section and boot sect ion can also be used for general application software. figure 7-1. flash program memory (hexadecimal address) word address 0 application section (256 kb/192 kb/128 kb/64 kb) ... 1efff / 16fff / efff / 77ff 1f000 / 17000 / f000 / 7800 application table section (8 kb/8 kb/8 kb/4 kb) 1ffff / 17fff / ffff / 7fff 20000 / 18000 / 10000 / 8000 boot section (8 kb/8 kb/8 kb/4 kb) 20fff / 18fff / 10fff / 87ff
11 8068t?avr?12/10 xmega a3 7.4 data memory the data memory consist of the i/o memory, eeprom and sram memories, all within one lin- ear address space, see figure 7-2 on page 11 . to simplify development, the memory map for all devices in the family is identical and with empt y, reserved memory space for smaller devices. figure 7-2. data memory map (hexadecimal address) byte address atxmega192a3 byte address ATXMEGA128A3 byte address atxmega64a3 0 i/o registers (4 kb) 0 i/o registers (4 kb) 0 i/o registers (4 kb) fff fff fff 1000 eeprom (2 kb) 1000 eeprom (2 kb) 1000 eeprom (2 kb) 17ff 17ff 17ff reserved reserved reserved 2000 internal sram (16 kb) 2000 internal sram (8 kb) 2000 internal sram (4 kb) 5fff 3fff 2fff byte address atxmega256a3 0 i/o registers (4 kb) fff 1000 eeprom (4 kb) 1fff 2000 internal sram (16 kb) 5fff
12 8068t?avr?12/10 xmega a3 7.4.1 i/o memory all peripherals and modules are addressable through i/o memory locations in the data memory space. all i/o memory locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, transferring data between the 32 general purpose registers in the cpu and the i/o memory. the in and out instructions can address i/o memory locations in the range 0x00 - 0x3f directly. i/o registers within the address range 0x00 - 0x1f are directly bit-acce ssible using the sbi and cbi instructions. the value of single bits can be checked by using the sbis and sbic instruc- tions on these registers. the i/o memory address for all peripherals and modules in xmega a3 is shown in the ?periph- eral module address map? on page 56 . 7.4.2 sram data memory the xmega a3 devices have internal sram memory for data storage. 7.4.3 eeprom data memory the xmega a3 devices have internal eeprom me mory for non-volatile data storage. it is addressable either in a separate data space or it can be memory mapped into the normal data memory space. the eeprom memory supports both byte and page access.
13 8068t?avr?12/10 xmega a3 7.5 production signature row the production signature row is a separate memory section for factory programmed data. it contains calibration data for functions such as oscillators and analog modules. the production signature row also contains a dev ice id that identify each microcontroller device type, and a serial number that is unique for each manufactured device. the device id for the available xmega a3 devices is shown in table 7-1 on page 13 . the serial number consist of the production lot number, wafer number, and wafer coordinates for the device. the production signature row can not be written or erased, but it can be read from both applica- tion software and external programming. table 7-1. device id bytes for xmega a3 devices. 7.6 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programming. the user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase session and on-chip debug sessions. device device id bytes byte 2 byte 1 byte 0 atxmega64a3 42 96 1e ATXMEGA128A3 42 97 1e atxmega192a3 44 97 1e atxmega256a3 42 98 1e
14 8068t?avr?12/10 xmega a3 7.7 flash and eeprom page size the flash program memory and eeprom data memory are organize d in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 7-2 on page 14 shows the flash program memory organization. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the most significant bits in the address (fpage) gives the page number and the least significant address bits (f w ord) gives the word in the page. table 7-2. number of words and pages in the flash. table 7-3 on page 14 shows eeprom memory organiza tion for the xmega a3 devices. eeeprom write and erase operatio ns can be perfo rmed one page or one by te at a time, while reading the eeprom is done one byte at a ti me. for eeprom access the nvm address regis- ter (addr[m:n]) is used for addre ssing. the most significant bits in the address (e2page) gives the page number and the least significant address bits (e2byte) gives the byte in the page. table 7-3. number of bytes and pages in the eeprom. devices flash page size fword fpage application boot size (words) size no of pages size no of pages atxmega64a3 64 kb + 4 kb 128 z[7:1] z[16:8] 64k 256 4 kb 16 ATXMEGA128A3 128 kb + 8 kb 256 z[8:1] z[17:9] 128k 256 8 kb 16 atxmega192a3 192 kb + 8 kb 256 z[8:1] z[18:9] 192k 384 8 kb 16 atxmega256a3 256 kb + 8 kb 256 z[8:1] z[18:9] 256k 512 8 kb 16 devices eeprom page size e2byte e2page no of pages size (bytes) atxmega64a3 2 kb 32 addr[4:0] addr[10:5] 64 ATXMEGA128A3 2 kb 32 addr[4:0] addr[10:5] 64 atxmega192a3 2 kb 32 addr[4:0] addr[10:5] 64 atxmega256a3 4 kb 32 addr[4:0] addr[11:5] 128
15 8068t?avr?12/10 xmega a3 8. dmac - direct memory access controller 8.1 features ? allows high-speed data transfer ? from memory to peripheral ? from memory to memory ? from peripheral to memory ? from peripheral to peripheral ? 4 channels ? from 1 byte and up to 16 m bytes transfers in a single transaction ? multiple addressing modes for so urce and destination address ?increment ? decrement ? static ? 1, 2, 4, or 8 bytes burst transfers ? programmable priority between channels 8.2 overview the xmega a3 has a direct memory access (dma) controller to move data between memories and peripherals in the data space. the dma controller uses the same data bus as the cpu to transfer data. it has 4 channels that can be configured independently. each dma channel can perform data transfers in blocks of configurable size from 1 to 64k bytes. a repeat counter can be used to repeat each block transfer for single transactions up to 16m bytes. each dma channel can be configured to access the source and destination memory address with incrementing, decrement- ing or static addressing. the addressing is independent for source and destination address. w hen the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction. the dmac can access all the peripherals through their i/o memory registers, and the dma may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from adc conversions, data transfer to dac conversions, or data transfer to or from port pins. a wide range of transfer triggers is available from the peripherals, event system and software. each dma channel has different transfer triggers. to allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. the dma controller can read from memory ma pped eeprom, but it cannot write to the eeprom or access the flash.
16 8068t?avr?12/10 xmega a3 9. event system 9.1 features ? inter-peripheral communication and signalling with minimum latency ? cpu and dma independent operation ? 8 event channels allows for up to 8 signals to be rout ed at the same time ? events can be generated by ? timer/counters (tcxn) ? real time counter (rtc) ? analog to digital converters (adcx) ? analog comparators (acx) ? ports (portx) ? system clock (clk sys ) ? software (cpu) ? events can be used by ? timer/counters (tcxn) ? analog to digital converters (adcx) ? digital to analog converters (dacx) ? ports (portx) ? dma controller (dmac) ? ir communication module (ircom) ? the same event can be used by multip le peripherals for synchronized timing ? advanced features ? manual event generati on from software (cpu) ? quadrature decoding ? digital filtering ? functions in active and idle mode 9.2 overview the event system is a set of features for inter-peripheral communication. it enables the possibil- ity for a change of state in one peripheral to automatically trigger actions in one or more peripherals. w hat changes in a periph eral that will trigger actions in other peripherals are config- urable by software. it is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, cpu or dma resources. the indication of a change in a peripheral is re ferred to as an event, and is usually the same as the interrupt conditions for that peripheral. events are passed between peripherals using a dedi- cated routing network called the event routing network. figure 9-1 on page 17 shows a basic block diagram of the event system with the event routing network and the peripherals to which it is connected. this highly flexible system can be used for simple routing of signals, pin func- tions or for sequencing of events. the maximum latency is two cpu clock cycles from when an event is generated in one periph- eral, until the actions are triggered in one or more other peripherals. the event system is functional in both active and idle modes.
17 8068t?avr?12/10 xmega a3 figure 9-1. event system block diagram. the event routing network can directly connect together adcs, dacs, analog comparators (acx), i/o ports (portx), the real-time counter (rtc), timer/counters (t/c) and the ir com- munication module (ircom). events can also be generated from software (cpu). all events from all peripherals are always routed into the event routing network. this consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. all eight event channels are connected to the peripherals that can use events, and each of these peripherals can be co nfigured to use events from one or more event channels to automatically trigger a software selectable action. adcx dacx event routing network portx cpu acx rtc t/cxn dmac ircom clk sys
18 8068t?avr?12/10 xmega a3 10. system clock and clock options 10.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32 mhz run-time cal ibrated rc oscillator ? 2 mhz run-time calibrated rc oscillator ? 32.768 khz calibrated rc oscillator ? 32 khz ultra low power (ulp) oscillator ? external clock options ? 0.4 - 16 mhz crystal oscillator ? 32.768 khz crystal oscillator ? external clock ? pll with internal and external clock options with 2 to 31x multiplication ? clock prescalers with 2 to 2048x division ? fast peripheral clock running at 2 and 4 times the cpu clock speed ? automatic run-time calibration of internal oscillators ? crystal oscillator failure detection 10.2 overview xmega a3 has an advanced clock system, supporting a large number of clock sources. it incor- porates both int egrated oscillators, external crystal osc illators and resonators . a high frequency phase locked loop (pll) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input. it is possible to switch between clock sources from software during run-time. after reset the device will always start up running fr om the 2 mhz inte rnal oscillator. a calibration feature is available, and can be used for automatic run-time calibration of the inter- nal 2 mhz and 32 mhz oscillators . this reduce frequency drift over voltage and temperature. a crystal oscillator failure m onitor can be enabled to issue a non-maskable interrupt and switch to internal oscillator if the external oscillator fails. figure 10-1 on page 19 shows the prin- cipal clock system in xmega a3.
19 8068t?avr?12/10 xmega a3 figure 10-1. clock system overview each clock source is briefly described in th e following sub-sections. 10.3 clock options 10.3.1 32 khz ultra low power internal oscillator the 32 khz ultra low power (ulp) internal oscillator is a very low power consumption clock source. it is used for the w atchdog timer, brown-out detecti on and as an asynchronous clock source for the real time counter. this oscill ator cannot be used as the system clock source, and it cannot be directly controlled from software. 10.3.2 32.768 khz calibrated internal oscillator the 32.768 khz calibrated internal oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the real time counter. it is calibrated during production to provide a default frequency which is close to its nominal frequency. 32 mhz run-time calibrated internal oscillator 32 khz ulp internal oscillator 32.768 khz calibrated internal oscillator 32.768 khz crystal oscillator 0.4 - 16 mhz crystal oscillator 2 mhz run-time calibrated internal oscillator external clock input clock control unit with pll and prescaler wdt/bod clk ulp rtc clk rtc evsys peripherals adc dac ports ... clk per dma interrupt ram nvm memory flash eeprom cpu clk cpu
20 8068t?avr?12/10 xmega a3 10.3.3 32.768 khz crystal oscillator the 32.768 khz crystal oscillator is a low power driver for an external watch crystal. it can be used as system clock source or as asynchrono us clock source for the real time counter. 10.3.4 0.4 - 16 mhz crystal oscillator the 0.4 - 16 mhz crystal oscillator is a driver in tended for driving both external resonators and crystals ranging from 400 khz to 16 mhz. 10.3.5 2 mhz run-time calibrated internal oscillator the 2 mhz run-time calibrated internal oscillato r is a high frequency oscillator. it is calibrated during production to provide a def ault frequency which is close to its nominal frequency. the oscillator can use the 32.768 khz calibrated inter nal oscillator or the 32 khz crystal oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.6 32 mhz run-time calibrated internal oscillator the 32 mhz run-time calibrated inte rnal oscillator is a high frequen cy oscillator. it is calibrated during production to provide a def ault frequency which is close to its nominal frequency. the oscillator can use the 32.768 khz calibrated inter nal oscillator or the 32 khz crystal oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.7 external clock input the external clock input gives the possibility to connect a clock from an external source. 10.3.8 pll with multiplication factor 1 - 31x the pll provides the possibility of multiplying a frequency by any number from 1 to 31. in com- bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
21 8068t?avr?12/10 xmega a3 11. power management and sleep modes 11.1 features ? 5 sleep modes ?idle ? power-down ?power-save ?standby ? extended standby ? power reduction registers to disable clocks to unused peripherals 11.2 overview the xmega a3 provides various sleep modes tailo red to reduce power consumption to a mini- mum. all sleep modes are available and can be entered from active mode. in active mode the cpu is executing application code. the applicat ion code decides when and which sleep mode to enter. interrupts from enabled peripherals and all enabled reset sources can restore the micro- controller from sleep to active mode. in addition, power reduction registers provide a method to stop the clock to individual peripher- als from software. w hen this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep mode. 11.3 sleep modes 11.3.1 idle mode in idle mode the cpu and non-volatile memory are stopped, but all peripherals including the interrupt controller, event system and dma controller are kept running. interrupt requests from all enabled in terrupts will wake the device. 11.3.2 power-down mode in power-down mode all system clock sources, and the asynchronous real time counter (rtc) clock source, are stopped. this allows operatio n of asynchronous modules only. the only inter- rupts that can wake up the mcu are the two w ire interface address match interrupts, and asynchronous port interrupts, e.g pin change. 11.3.3 power-save mode power-save mode is identical to power-down, with one exception: if the rtc is enabled, it will keep running during sleep and the device can also wake up from rtc interrupts. 11.3.4 standby mode standby mode is identical to power-down with the exception that all enabled system clock sources are kept running, while the cpu, periph eral and rtc clocks are stopped. this reduces the wake-up time when external crystals or resonators are used.
22 8068t?avr?12/10 xmega a3 11.3.5 extended standby mode extended standby mode is identical to power-sav e mode with the exception that all enabled system clock sources are kept ru nning while the cpu and periph eral clocks are stopped. this reduces the wake-up time when external crystals or resonators are used.
23 8068t?avr?12/10 xmega a3 12. system control and reset 12.1 features ? multiple reset sources for safe operation and device reset ? power-on reset ? external reset ? watchdog reset the watchdog timer runs from separate, dedica ted oscillator ? brown-out reset accurate, programmable brown-out levels ? pdi reset ? software reset ? asynchronous reset ? no running clock in the device is required for reset ? reset status register 12.2 resetting the avr during reset, all i/o registers are set to their initial values. the sram content is not reset. appli- cation execution starts from the reset vector. the instruction placed at the reset vector should be an absolute jump (jmp) instruction to the reset handling routine. by default the reset vector address is the lowest flash program memory address, ?0?, but it is possible to move the reset vector to the first address in the boot section. the i/o ports of the avr are immediately tri-stated when a reset source goes active. the reset functionality is asynchronous, so no running cl ock is required to reset the device. after the device is reset, the reset source can be determined by the application by reading the reset sta- tus register. 12.3 reset sources 12.3.1 power-on reset the mcu is reset when the supp ly voltage vcc is below the po wer-on reset threshold voltage. 12.3.2 external reset the mcu is reset when a low leve l is present on the reset pin. 12.3.3 watchdog reset the mcu is reset when the w atchdog timer period expires and the w atchdog reset is enabled. the w atchdog timer runs from a dedicated oscillator independent of the system clock. for more details see ? w dt - w atchdog timer? on page 24 . 12.3.4 brown-out reset the mcu is reset when the supply voltage vcc is below the brown-out reset threshold voltage and the brown-out detector is enabled. the brown-out threshold voltage is programmable. 12.3.5 pdi reset the mcu can be reset through the program and debug interface (pdi).
24 8068t?avr?12/10 xmega a3 12.3.6 software reset the mcu can be reset by the cpu writing to a special i/o register through a timed sequence. 13. wdt - watchdog timer 13.1 features ? 11 selectable timeout periods, from 8 ms to 8s. ? two operation modes ? standard mode ? window mode ? runs from the 1 khz output of th e 32 khz ultra low power oscillator ? configuration lock to prevent unwanted changes 13.2 overview the xmega a3 has a w atchdog timer ( w dt). the w dt will run continuous ly when turned on and if the w atchdog timer is not reset within a software configurable time-out period, the micro- controller will be reset. the w atchdog reset ( w dr) instruction must be ru n by software to reset the w dt, and prevent microcontroller reset. the w dt has a w indow mode. in this mode the w dr instruction must be run within a specified period called a window. application software can set the minimum and maximum limits for this window. if the w dr instruction is not executed inside t he window limits, the microcontroller will be reset. a protection mechanism using a timed write se quence is implemented in order to prevent unwanted enabling, disabling or change of w dt settings. for maximum safety, the w dt also has an always-on mode. this mode is enabled by program- ming a fuse. in always-on mode, application software can not disable the w dt.
25 8068t?avr?12/10 xmega a3 14. pmic - programmable mult i-level interrupt controller 14.1 features ? separate interrupt vector for each interrupt ? short, predictable in terrupt response time ? programmable multi-level interrupt controller ? 3 programmable interrupt levels ? selectable priority scheme within low level interrupts (round-robin or fixed) ? non-maskable interrupts (nmi) ? interrupt vectors can be moved to the start of the boot section 14.2 overview xmega a3 has a programmable multi-level interrupt controller (pmic). all peripherals can define three different priority levels for interrupts; high, medium or low. medium level interrupts may interrupt low level interrupt service routines. high level interrupts may interrupt both low- and medium level interrupt service routines. low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time. the built in oscillator failure detection mechanism can issue a non-maskable interrupt (nmi). 14.3 interrupt vectors w hen an interrupt is serviced, t he program counter will ju mp to the interrupt vector address. the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the xmega a3 devices are shown in table 14-1 . offset addresses for each interrupt available in the peripheral are described for each peripheral in the xmega a manual. for peripherals or modules that have only one inter- rupt, the interrupt vector is shown in table 14-1 . the program address is the word address. table 14-1. reset and interrupt vectors program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillato r failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base 0x008 portr_int_base port r interrupt base 0x00c dma_int_base dma controller interrupt base 0x014 rtc_int_base real time counter interrupt base 0x018 t w ic_int_base two- w ire interface on port c interrupt base 0x01c tcc0_int_base timer/counter 0 on port c interrupt base 0x028 tcc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x03d usartc1_int_base usart 1 on port c interrupt base 0x03e aes_int_vect aes interrupt vector
26 8068t?avr?12/10 xmega a3 0x040 nvm_int_base non-volatile memory interrupt base 0x044 portb_int_base port b interrupt base 0x048 acb_int_base analog comparator on port b interrupt base 0x04e adcb_int_base analog to digital converter on port b interrupt base 0x056 porte_int_base port e int base 0x05a t w ie_int_base two- w ire interface on port e interrupt base 0x05e tce0_int_base timer/counter 0 on port e interrupt base 0x06a tce1_int_base timer/counter 1 on port e interrupt base 0x072 spie_int_vect spi on port e interrupt vector 0x074 usarte0_int_base usart 0 on port e interrupt base 0x07a usarte1_int_base usart 1 on port e interrupt base 0x080 portd_int_base port d interrupt base 0x084 porta_int_base port a interrupt base 0x088 aca_int_base analog comparator on port a interrupt base 0x08e adca_int_base analog to digital converter on port a interrupt base 0x09a tcd0_int_base timer/counter 0 on port d interrupt base 0x0a6 tcd1_int_base timer/counter 1 on port d interrupt base 0x0ae spid_int_vector spi d interrupt vector 0x0b0 usartd0_int_base usart 0 on port d interrupt base 0x0b6 usartd1_int_base usart 1 on port d interrupt base 0x0d0 portf_int_base port f interrupt base 0x0d8 tcf0_int_base timer/counter 0 on port f interrupt base 0x0ee usartf0_int_base usart 0 on port f interrupt base table 14-1. reset and interrupt vectors (continued) program address (base address) source interrupt description
27 8068t?avr?12/10 xmega a3 15. i/o ports 15.1 features ? selectable input and output configuration for each pin individually ? flexible pin configuration through dedicated pin configuration register ? synchronous and/or asynchronous input sensing with port interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? asynchronous wake-up from all input sensing configurations ? two port interrupts with flexible pin masking ? highly configurable output driver and pull settings: ? totem-pole ? pull-up/-down ? wired-and ? wired-or ? bus-keeper ? inverted i/o ? configuration of multiple pins in a single operation ? read-modify-write (rmw) support ? toggle/clear/set registers for output and direction registers ? clock output on port pin ? event channel 0 output on port pin 7 ? mapping of port registers (virtual port s) into bit accessible i/o memory space 15.2 overview the xmega a3 devices have flexible general purpose i/o ports. a port consists of up to 8 pins, ranging from pin 0 to pin 7. the ports implemen t several functions, including synchronous/asyn- chronous input sensing, pin change interrupts and configurable output settings. all functions are individual per pin, but several pins may be configured in a single operation. 15.3 i/o configuration all port pins (pn) have programmable output configuration. in addition, all port pins have an inverted i/o function. for an input, this means in verting the signal between the port pin and the pin register. for an output, this means invert ing the output signal between the port register and the port pin. the inverted i/o function can be used also when the pin is used for alternate functions.
28 8068t?avr?12/10 xmega a3 15.3.1 push-pull figure 15-1. i/o configuration - totem-pole 15.3.2 pull-down figure 15-2. i/o configuration - totem-pole with pull-down (on input) 15.3.3 pull-up figure 15-3. i/o configuration - totem-pole with pull-up (on input) 15.3.4 bus-keeper the bus-keeper?s weak output produces the same logi cal level as the last output level. it acts as a pull-up if the last leve l was ?1?, and pull-down if the last level was ?0?. inn outn dirn pn inn outn dirn pn inn outn dirn pn
29 8068t?avr?12/10 xmega a3 figure 15-4. i/o configuration - totem-pole with bus-keeper 15.3.5 others figure 15-5. output configuration - w ired-or with optional pull-down figure 15-6. i/o configuration - w ired-and with optional pull-up inn outn dirn pn inn outn pn inn outn pn
30 8068t?avr?12/10 xmega a3 15.4 input sensing ? sense both edges ? sense rising edges ? sense falling edges ? sense low level input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 15-7 on page 30 . figure 15-7. input sensing system overview w hen a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 15.5 port interrupt each port has two interrupts with separate priority and interrupt vector. all pins on the port can be individually selected as source for each of the interrupts. the interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt. 15.6 alternate port functions in addition to the input/output functions on all po rt pins, most pins have alternate functions. this means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. ?pinout and pin functions? on page 49 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
31 8068t?avr?12/10 xmega a3 16. t/c - 16-bits time r/counter with pwm 16.1 features ? seven 16-bit timer/counters ? four timer/counters of type 0 ? three timer/counters of type 1 ? four compare or capture (cc) channels in timer/counter 0 ? two compare or capture (cc) channels in timer/counter 1 ? double buffered timer period setting ? double buffered compare or capture channels ? waveform generation: ? single slope pulse width modulation ? dual slope pulse width modulation ? frequency generation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? event counter with direction control ? timer overflow and timer error interrupts and events ? one compare match or capture interrupt and event per cc channel ? supports dma operation ? hi-resolution extension (hi-res) ? advanced waveform extension (awex) 16.2 overview xmega a3 has seven timer/counters, four timer/counter 0 and three timer/counter 1. the difference between them is that timer/counter 0 has four compare/capture channels, while timer/counter 1 has two compare/capture channels. the timer/counters (t/c) are 16-bit and can count any clock, event or external input in the microcontroller. a programmable prescaler is available to get a useful t/c resolution. updates of timer and compare registers are double buffered to ensure glitch free operation. single slope p w m, dual slope p w m and frequency generation waveforms can be generated using the com- pare channels. through the event system, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is requir ed for this. the input capture has a noise cancel- ler to avoid incorrect capture of the t/c, and can be used to do frequency and pulse width measurements. a wide range of interrupt or event sources ar e available, including t/c overflow, compare match and capture for each compare/capture channel in the t/c. portc, portd and porte each has one timer/counter 0 and one timer/counter1. portf has one timer/counter 0. notation of these are tcc0 (time/counter c0), tcc1, tcd0, tcd1, tce0, tce1 and tcf0, respectively.
32 8068t?avr?12/10 xmega a3 figure 16-1. overview of a timer/counter and closely related peripherals the hi-resolution extension can be enabled to increase the waveform generation resolution by 2 bits (4x). this is available for all timer/counters. see ?hi-res - high resolution extension? on page 34 for more details. the advanced w aveform extension can be enabled to provide extra and more advanced fea- tures for the timer/counter. this are only available for timer/counter 0. see ?a w ex - advanced w aveform extension? on page 33 for more details. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dti dead-time insertion pattern generation clk per4 port event system clk per timer/counter
33 8068t?avr?12/10 xmega a3 17. awex - advanced waveform extension 17.1 features ? output with complementary output from each capture channel ? four dead time insertion (dti) un its, one for each capture channel ? 8-bit dti resolution ? separate high and low side dead-time setting ? double buffered dead-time ? event controlled fault protection ? single channel multiple output operation (for bldc motor control) ? double buffered pattern generation 17.2 overview the advanced w aveform extension (a w ex) provides extra features to the timer/counter in w aveform generation ( w g) modes. the a w ex enables easy and safe implementation of for example, advanced motor control (ac, bldc, sr , and stepper) and power control applications. any w g output from a timer/counter 0 is split into a complimentary pair of outputs when any a w ex feature is enabled. these output pairs go through a dead-time insertion (dti) unit that enables generation of the non-inverted low side (ls) and inverted high side (hs) of the w g output with dead time insertion between ls and hs switching. the dti output will override the normal port value according to the port override setting. optionally the final output can be inverted by using the invert i/o setting for the port pin. the pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. in addition, the waveform generator output from compare channel a can be dis- tributed to, and override all port pins. w hen the pattern generator unit is enabled, the dti unit is bypassed. the fault protection unit is connected to the ev ent system. this enables any event to trigger a fault condition that will disable the a w ex output. several event channels can be used to trigger fault on several different conditions. the a w ex is available for tcc0. the notation of this is a w exc.
34 8068t?avr?12/10 xmega a3 18. hi-res - high r esolution extension 18.1 features ? increases waveform generator resolution by 2-bits (4x) ? supports frequency, single- and dual-slope pwm operation ? supports the awex when this is enable d and used for the same timer/counter 18.2 overview the hi-resolution (hi-res) extension is able to increase the resolution of the waveform genera- tion output by a factor of 4. w hen enabled for a timer/counter, the fast peripheral clock running at four times the cpu clock speed will be as input to th e timer/counter. the high resolution extension can also be used when an a w ex is enabled and used with a timer/counter. xmega a3 devices have four hi-res extensions that each can be enabled for each timer/counters pair on portc, portd, porte and portf. the notation of these are hiresc, hiresd, hirese and hiresf, respectively.
35 8068t?avr?12/10 xmega a3 19. rtc - real-time counter 19.1 features ? 16-bit timer ? flexible tick resolution ranging from 1 hz to 32.768 khz ? one compare register ? one period register ? clear timer on overflow or compare match ? overflow or compare match event and interrupt generation 19.2 overview the xmega a3 includes a 16-bit real-time count er (rtc). the rtc can be clocked from an accurate 32.768 khz crystal osc illator, the 32.768 khz ca librated internal osc illator, or from the 32 khz ultra low power internal oscillator. the rtc includes both a period and a compare register. for details, see figure 19-1 . a wide range of resolution and time-out periods can be configured using the rtc. w ith a max- imum resolution of 30.5 s, time-out periods range up to 2000 seconds. w ith a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds). figure 19-1. real-time counter overview 10-bit prescaler counter period compare = = overflow compare match 1.024 khz 32.768 khz
36 8068t?avr?12/10 xmega a3 20. twi - two wire interface 20.1 features ? two identical twi peripherals ? simple yet powerful and flexible communication interface ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes w ake-up when in sleep mode ? i 2 c and system management bus (smbus) compatible 20.2 overview the two- w ire interface (t w i) is a bi-directional wired-and bus with only two lines, the clock (scl) line and the data (sda) line. the protocol makes it possible to interconnect up to 128 indi- vidually addressable devices. since it is a mult i-master bus, one or more devices capable of taking control of the bus can be connected. the only external hardware needed to implement the bus is a single pull-up resistor for each of the t w i bus lines. mechanisms for resolving bus contention are inherent in the t w i protocol. portc and porte each has one t w i. notation of these peripherals are t w ic and t w ie.
37 8068t?avr?12/10 xmega a3 21. spi - serial peripheral interface 21.1 features ? three identical spi peripherals ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 21.2 overview the serial peripheral interface (spi) allows high-speed full-duplex, synchronous data transfer between different devices. devices can communica te using a master-slave scheme, and data is transferred both to and from the devices simultaneously. portc, portd, and porte each has one spi. notation of these peripherals are spic, spid, and spie respectively.
38 8068t?avr?12/10 xmega a3 22. usart 22.1 features ? seven identical usart peripherals ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high-resolution arithmetic baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode ? master spi mode for spi communication ? irda support through the ircom module 22.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communica tion module. the usart supports full duplex communication, and both asynchronous and clocked synchronous operation. the usart can also be set in master spi mode to be used for spi communication. communication is frame based, and the frame format can be customized to support a wide range of standards. the usart is buffered in both direction, enabling continued data transmis- sion without any delay between frames. there are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. frame error and buffer over- flow are detected in hardware and indicated with separate status flags. even or odd parity generation and parity check can also be enabled. one usart can use the ircom module to suppor t irda 1.4 physical compliant pulse modula- tion and demodulation for baud rates up to 115.2 kbps. portc, portd, and porte each has two usarts, while portf has one usart only. notation of these peripherals are usartc0, usartc1, usartd0, usartd1, usarte0, usarte1 and usartf0, respectively.
39 8068t?avr?12/10 xmega a3 23. ircom - ir communication module 23.1 features ? pulse modulation/demodulation for infrared communication ? compatible to irda 1.4 physical for baud rates up to 115.2 kbps ? selectable pulse modulation scheme ? 3/16 of baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built in filtering ? can be connected to and used by one usart at a time 23.2 overview xmega contains an infrared communication module (ircom) for irda communication with baud rates up to 115.2 kbps. this supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the peripheral clock speed, or pulse modulation dis- abled. there is one ircom available which can be connected to any usart to enable infrared pulse coding/decoding for that usart.
40 8068t?avr?12/10 xmega a3 24. crypto engine 24.1 features ? data encryption standard (des) cpu instruction ? advanced encryption stan dard (aes) crypto module ? des instruction ? encryption and decryption ? single-cycle des instruction ? encryption/decryption in 16 clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? support 128-bit keys ? support xor data load mode to the state memory for cipher block chaining ? encryption/decryption in 375 clock cycles per 16-byte block 24.2 overview the advanced encrypti on standard (aes) and da ta encryption standar d (des) are two com- monly used encryption st andards. these ar e supported through an aes peripheral module and a des cpu instruction. all communication inte rfaces and the cpu ca n optionally use aes and des encrypted communication and data storage. des is supported by a des instruction in the avr xmega cpu. the 8-byte key and 8-byte data blocks must be loade d into the register file, and then des must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. the key and data must be loaded into the key and state memory in the module before encryp- tion/decryption is started. it takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. the aes crypto module also has dma support wit h transfer triggers wh en encryption/decryp- tion is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
41 8068t?avr?12/10 xmega a3 25. adc - 12-bit analog to digital converter 25.1 features ? two adcs with 12-bit resolution ? 2 msps sample rate for each adc ? signed and unsign ed conversions ? 4 result registers with individual input channel control for each adc ? 8 single ended inputs for each adc ? 8x4 differential inputs for each adc ? 4 internal inputs: ? integrated temperature sensor ? dac output ? vcc voltage divided by 10 ? bandgap voltage ? software selectable gain of 2, 4, 8, 16, 32 or 64 ? software selectable resolution of 8- or 12-bit. ? internal or external reference selection ? event triggered conversion for accurate timing ? dma transfer of conversion results ? interrupt/event on compare result 25.2 overview xmega a3 devices have two analog to digital converters (adc), see figure 25-1 on page 42 . the two adc modules can be operated simult aneously, individually or synchronized. the adc converts analog voltages to digital values. the adc has 12-bit resolution and is capa- ble of converting up to 2 millio n samples per second. the input selection is flexible, and both single-ended and differential measurements can be done. for differential measurements an optional gain stage is available to increase the dynamic range. in addition several internal signal inputs are available. the adc can provide both signed and unsigned results. this is a pipeline adc. a pipeline adc consis ts of several consecutive stages, where each stage convert one part of the result. the pipeline design enables high sample rate at low clock speeds, and remove limitations on samples spee d versus propagation delay. this also means that a new analog voltage can be sampled and a new adc measurement started while other adc measurements are ongoing. adc measurements can either be started by application software or an incoming event from another peripheral in the device. four different result registers with individual input selection (mux selection) are provided to make it easier for the application to keep track of the data. each result register and mux selection pair is referred to as an adc channel. it is possible to use dma to move adc results directly to memory or peripherals when conversions are done. both internal and external analog reference volt ages can be used. an accurate internal 1.0v reference is available. an integrated temperature sensor is available and the output from this can be measured with the adc. the output from the dac, vcc/10 and the bandgap voltage can also be measured by the adc.
42 8068t?avr?12/10 xmega a3 figure 25-1. adc overview each adc has four mux selection registers with a corresponding result register. this means that four channels can be sampled within 1.5 s without any intervention by the application other than starting the conversion . the results will be availabl e in the result registers. the adc may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) from 3.5 s for 12-bit to 2.5 s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). porta and portb each has one adc. notation of these peripherals are adca and adcb, respectively. adc channel a register channel b register channel c register channel d register pin inputs pin inputs 1-64 x internal inputs channel a mux selection channel b mux selection channel c mux selection channel d mux selection event trigger configuration reference selection
43 8068t?avr?12/10 xmega a3 26. dac - 12-bit digital to analog converter 26.1 features ? one dac with 12-bit resolution ? up to 1 msps conversion rate for each dac ? flexible conversion range ? multiple trigger sources ? 1 continuous output or 2 sample and hold (s/h) outputs for each dac ? built-in offset an d gain calibration ? high drive capabilities ? low power mode 26.2 overview the xmega a3 features one two-channel, 12-bit, 1 msps dacs with built-in offset and gain cal- ibration, see figure 26-1 on page 43 . a dac converts a digital value into an anal og signal. the dac may use an internal 1.0 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. the external reference input is shared with the adc reference input. figure 26-1. dac overview the dac has one cont inuous output with high drive capab ilities for both resi stive and capacitive loads. it is also possible to split the continuous time channel into two sample and hold (s/h) channels, each with separate data conversion registers. a dac conversion may be started from the applic ation software by writing the data conversion registers. the dac can also be configured to do conversions triggered by the event system to have regular timing, independent of the application software. dma may be used for transferring data from memory locations to dac data registers. the dac has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. portb each has one dac. notation of this peripheral is dacb. dac channel a register channel b register event trigger configuration reference selection channel a channel b
44 8068t?avr?12/10 xmega a3 27. ac - analog comparator 27.1 features ? four analog comparators ? selectable power vs. speed ? selectable hysteresis ? 0, 20 mv, 50 mv ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? output from the dac ? bandgap reference voltage. ? voltage scaler that can perform a 64-le vel scaling of the internal vcc voltage. ? interrupt and event generation on ? rising edge ? falling edge ?toggle ? window function interrupt and event generation on ? signal above window ? signal inside window ? signal below window 27.2 overview xmega a3 features four analog comparators (ac). an analog comparator compares two volt- ages, and the output indicates which input is largest. the analog comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application. a wide range of input selection is available, both external pins and several internal signals can be used. the analog comparators are always grouped in pairs (ac0 and ac1) on each analog port. they have identical behavior but separate control registers. optionally, the state of the comparator is directly available on a pin. porta and portb each has one ac pair. notations are aca and acb, respectively.
45 8068t?avr?12/10 xmega a3 figure 27-1. analog comparator overview ac0 + - pin inputs internal inputs pin inputs internal inputs vcc scaled interrupt sensitivity control interrupts ac1 + - pin inputs internal inputs pin inputs internal inputs vcc scaled events pin 0 output
46 8068t?avr?12/10 xmega a3 27.3 input selection the analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. one pair of analog comparators is shown in figure 27-1 on page 45 . ? input selection from pin ? pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator ? pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator ? internal signals available on positive analog comparator inputs ? output from 12-bit dac ? internal signals available on ne gative analog comparator inputs ? 64-level scaler of the vcc, available on negative analog comparator input ? bandgap voltage reference ? output from 12-bit dac 27.4 window function the window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in figure 27-2 . figure 27-2. analog comparator window function ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
47 8068t?avr?12/10 xmega a3 28. ocd - on-chip debug 28.1 features ? complete program flow control ? go, stop, reset, step into, step over, step out, run-to-cursor ? debugging on c and high-level language source code level ? debugging on assembler and disassembler level ? 1 dedicated program address or source level breakpoint for avr studio / debugger ? 4 hardware breakpoints ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, with break on: ? data location read, write or both read and write ? data location content equal or not equal to a value ? data location content is greater or less than a value ? data location content is within or outside a range ? bits of a data location are eq ual or not equal to a value ? non-intrusive operation ? no hardware or software resources in the device are used ? high speed operation ? no limitation on debug/programming clock frequency versus sys tem clock frequency 28.2 overview the xmega a3 has a powerful on-chip debug (ocd) system that - in combination with atmel?s development tools - provides all the necessary functions to debug an application. it has support for program and data breakpoints, and can debug an application from c and high level language source code level, as well as assembler and disassembler level. it has full non-intrusive opera- tion and no hardware or softw are resources in the device are used. the odc system is accessed through an external debugging tool which connects to the jtag or pdi physical inter- faces. refer to ?program and debug interfaces? on page 48 .
48 8068t?avr?12/10 xmega a3 29. program and debug interfaces 29.1 features ? pdi - program and debug interface (atmel proprietary 2-pin interface) ? jtag interface (ieee std. 1149.1 compliant) ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) ? access to the ocd system ? programming of flash, eepr om, fuses and lock bits 29.2 overview the programming and debug facilities are accessed through the jtag and pdi physical inter- faces. the pdi physical interface uses one dedicated pin together with the reset pin, and no general purpose pins are used. jtag uses four general purpose pins on portb. the pdi is an atmel proprietary protocol for communication between the microcontroller and atmel?s or third party development tools. 29.3 ieee 1149.1 (jtag) boundary-scan the jtag physical layer handles the basic low-level serial communication over four i/o lines named tms, tck, tdi, and tdo. it complies to the ieee std. 1149.1 for test access port and boundary scan. 29.3.1 boundary-scan order table 30-8 on page 53 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order. bit 4, 5, 6 and 7 of port b is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. 29.3.2 boundary-scan description language files boundary-scan description language (bsdl) files describe boundary-scan capable devices in a standard format used by automated test-generation software. the order and function of bits in the boundary-scan data register are included in th is description. bsdl files are available for atxmega256/192/128/64a3 devices. see table 30-8 on page 53 for atxmega256/192/128/64a3 boundary scan order.
49 8068t?avr?12/10 xmega a3 30. pinout and pin functions the pinout of xmega a3 is shown in ?? on page 2 . in addition to general i/o functionality, each pin may have several function. th is will depend on which peripheral is enabled and connected to the actual pin. only one of the alternate pin functions can be used at time. 30.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 30.1.1 operation/power supply 30.1.2 port interrupt functions 30.1.3 analog functions 30.1.4 timer/counter and awex functions vcc digital supply voltage avcc analog supply voltage gnd ground sync port pin with full synchronous and limited asynchronous interrupt function async port pin with full syn chronous and full asynchro nous interrupt function acn analog comparator input pin n ac0out analog comparator 0 output adcn analog to digital converter input pin n dacn digital to analog converter output pin n aref analog reference input pin ocnx output compare channel x for timer/counter n ocnx inverted output compare channel x for timer/counter n ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n
50 8068t?avr?12/10 xmega a3 30.1.5 communication functions 30.1.6 oscillators, clock and event 30.1.7 debug/system functions scl serial clock for t w i sda serial data for t w i sclin serial clock in for t w i when external driver interface is enabled sclout serial clock out for t w i when external driver interface is enabled sdain serial data in for t w i when external driver interface is enabled sdaout serial data out for t w i when external driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi toscn timer oscillator pin n xtaln input/output for inverting oscillator pin n clkout peripheral clock output evout event channel 0 output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin t c k j tag te s t c l o c k tdi jtag test data in t d o j tag te s t d a t a o u t t m s j tag te s t m o d e s e l e c t
51 8068t?avr?12/10 xmega a3 30.2 alternate pin functions the tables below show the main and alternate pin functions for all pins on each port. they also show which peripheral that makes use of or enables the alternate pin function. table 30-1. port a - alternate functions port a pin # interrupt adca pos adca neg adaa gainpos adca gainneg aca pos aca neg aca out refa gnd 60 avcc 61 pa0 62 sync adc0 adc0 adc0 ac0 ac0 aref pa1 63 sync adc1 adc1 adc1 ac1 ac1 pa2 64 sync/async adc2 adc2 adc2 ac2 pa3 1 sync adc3 adc3 adc3 ac3 ac3 pa4 2 sync adc4 adc4 adc4 ac4 pa5 3 sync adc5 adc5 adc5 ac5 ac5 pa6 4 sync adc6 adc6 adc6 ac6 pa7 5 sync adc7 adc7 adc7 ac7 ac0 out table 30-2. port b - alternate functions port b pin # interrupt adcb pos adcb neg adcb gainpos adcb gainneg acb pos acb neg acb out dacb refb jtag pb0 6 sync adc0 adc0 adc0 ac0 ac0 aref pb1 7 sync adc1 adc1 adc1 ac1 ac1 pb2 8 sync/async adc2 adc2 adc2 ac2 dac0 pb3 9 sync adc3 adc3 adc3 ac3 ac3 dac1 pb4 10 sync adc4 adc4 adc4 ac4 tms pb5 11 sync adc5 adc5 adc5 ac5 ac5 tdi pb6 12 sync adc6 adc6 adc6 ac6 tck pb7 13 sync adc7 adc7 adc7 ac7 ac0 out tdo gnd 14 vcc 15
52 8068t?avr?12/10 xmega a3 table 30-3. port c - alternate functions port c pin # interrupt tcc0 awexc tcc1 us artc0 usartc1 spic twic clockout eventout pc0 16 sync oc0a oc0als sda pc1 17 sync oc0b oc0ahs xck0 scl pc2 18 sync/async oc0c oc0bls rxd0 pc3 19 sync oc0d oc0bhs txd0 pc4 20 sync oc0cls oc1a ss pc5 21 sync oc0chs oc1b xck1 mosi pc6 22 sync oc0dls rxd1 miso pc7 23 sync oc0dhs txd1 sck clkout evout gnd 24 vcc 25 table 30-4. port d - alternate functions port d pin # interrupt tcd0 tcd1 usartd0 usartd1 spid clockout eventout pd0 26 sync oc0a pd1 27 sync oc0b xck0 pd2 28 sync/async oc0c rxd0 pd3 29 sync oc0d txd0 pd4 30 sync oc1a ss pd5 31 sync oc1b xck1 mosi pd6 32 sync rxd1 miso pd7 33 sync txd1 sck clkout evout gnd 34 vcc 35 table 30-5. port e - alternate functions port e pin # interrupt tce0 tce1 usarte0 usarte1 spie twie clockout eventout tosc pe0 36 sync oc0a sda pe1 37 sync oc0b xck0 scl pe2 38 sync/async oc0c rxd0 pe3 39 sync oc0d txd0 pe4 40 sync oc1a ss pe5 41 sync oc1b xck1 mosi pe6 42 sync rxd1 miso tosc2 pe7 43 sync txd1 sck clkout evout tosc1 gnd 44 vcc 45
53 8068t?avr?12/10 xmega a3 table 30-7. port r - alternate functions table 30-8. atxmega256/192/128/64a3 boundary scan order table 30-6. port f - alternate functions port f pin # interrupt tcf0 usartf0 pf0 46 sync oc0a pf1 47 sync oc0b xck0 pf2 48 sync/async oc0c rxd0 pf3 49 sync oc0d txd0 pf4 50 sync pf5 51 sync pf6 54 sync pf7 55 sync gnd 52 vcc 53 port r pin # interrupt progr xtal pdi 56 pdi_data reset 57 pdi_clock pro 58 sync xtal2 pr1 59 sync xtal1 bit number signal name module 149 pq3.bidir port q 148 pq3.control 147 pq2.bidir 146 pq2.control 145 pq1.bidir 144 pq1.control 143 pq0.bidir 142 pq0.control 141 pk7.bidir port k 140 pk7.control 139 pk6.bidir 138 pk6.control 137 pk5.bidir 136 pk5.control 135 pk4.bidir 134 pk4.control 133 pk3.bidir 132 pk3.control 131 pk2.bidir 130 pk2.control 129 pk1.bidir 128 pk1.control 127 pk0.bidir 126 pk0.control
54 8068t?avr?12/10 xmega a3 125 pj7.bidir port j 124 pj7.control 123 pj6.bidir 122 pj6.control 121 pj5.bidir 120 pj5.control 119 pj4.bidir 118 pj4.control 117 pj3.bidir 116 pj3.control 115 pj2.bidir 114 pj2.control 113 pj1.bidir 112 pj1.control 111 pj0.bidir 110 pj0.control 109 ph7.bidir port h 108 ph7.control 107 ph6.bidir 106 ph6.control 105 ph5.bidir 104 ph5.control 103 ph4.bidir 102 ph4.control 101 ph3.bidir 100 ph3.control 99 ph2.bidir 98 ph2.control 97 ph1.bidir 96 ph1.control 95 ph0.bidir 94 ph0.control 93 pf7.bidir port f 92 pf7.control 91 pf6.bidir 90 pf6.control 89 pf5.bidir 88 pf5.control 87 pf4.bidir 86 pf4.control 85 pf3.bidir 84 pf3.control 83 pf2.bidir 82 pf2.control 81 pf1.bidir 80 pf1.control 79 pf0.bidir 78 pf0.control 77 pe7.bidir port e 76 pe7.control 75 pe6.bidir 74 pe6.control 73 pe5.bidir 72 pe5.control 71 pe4.bidir 70 pe4.control 69 pe3.bidir 68 pe3.control 67 pe2.bidir 66 pe2.control 65 pe1.bidir 64 pe1.control 63 pe0.bidir 62 pe0.control bit number signal name module
55 8068t?avr?12/10 xmega a3 61 pd7.bidir port d 60 pd7.control 59 pd6.bidir 58 pd6.control 57 pd5.bidir 56 pd5.control 55 pd4.bidir 54 pd4.control 53 pd3.bidir 52 pd3.control 51 pd2.bidir 50 pd2.control 49 pd1.bidir 48 pd1.control 47 pd0.bidir 46 pd0.control 45 pc7.bidir port c 44 pc7.control 43 pc6.bidir 42 pc6.control 41 pc5.bidir 40 pc5.control 39 pc4.bidir 38 pc4.control 37 pc3.bidir 36 pc3.control 35 pc2.bidir 34 pc2.control 33 pc1.bidir 32 pc1.control 31 pc0.bidir 30 pc0.control 29 pb3.bidir port b 28 pb3.control 27 pb2.bidir 26 pb2.control 25 pb1.bidir 24 pb1.control 23 pb0.bidir 22 pb0.control 21 pa7.bidir port a 20 pa7.control 19 pa6.bidir 18 pa6.control 17 pa5.bidir 16 pa5.control 15 pa4.bidir 14 pa4.control 13 pa3.bidir 12 pa3.control 11 pa2.bidir 10 pa2.control 9 pa1.bidir 8 pa1.control 7 pa0.bidir 6 pa0.control 5 pr1.bidir port r 4pr1.control 3 pr0.bidir 2pr0.control 1 reset.observe_only reset 0 pdi_data.observe_only pdi data bit number signal name module
56 8068t?avr?12/10 xmega a3 31. peripheral modu le address map the address maps show the base address for each peripheral and module in xmega a3. for complete register description and summary for each peripheral module, refer to the xmega a manual. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 2 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32 mhz internal rc oscillator 0x0068 dfllrc2m dfll for the 2 mhz rc oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 w dt w atch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00c0 aes aes module 0x0100 dma dma controller 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0240 adcb analog to digital converter on port b 0x0320 dacb digital to analog converter on port b 0x0380 aca analog comparator pair on port a 0x0390 acb analog comparator pair on port b 0x0400 rtc real time counter 0x0480 t w ic two w ire interface on port c 0x04a0 t w ie two w ire interfaceon port e 0x0600 porta port a 0x0620 portb port b 0x0640 portc port c 0x0660 portd port d 0x0680 porte port e 0x06a0 portf port f 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 a w exc advanced w aveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08b0 usartc1 usart 1 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0900 tcd0 timer/counter 0 on port d 0x0940 tcd1 timer/counter 1 on port d 0x0990 hiresd high resolution extension on port d 0x09a0 usartd0 usart 0 on port d 0x09b0 usartd1 usart 1 on port d 0x09c0 spid serial peripheral interface on port d 0x0a00 tce0 timer/counter 0 on port e 0x0a40 tce1 timer/counter 1 on port e 0x0a80 a w exe advanced w aveform extensionon port e 0x0a90 hirese high resolution extension on port e 0x0aa0 usarte0 usart 0 on port e 0x0ab0 usarte1 usart 1 on oirt e 0x0ac0 spie serial peripheral interface on port e 0x0b00 tcf0 timer/counter 0 on port f 0x0b90 hiresf high resolution extension on port f 0x0ba0 usartf0 usart 0 on port f
57 8068t?avr?12/10 xmega a3 32. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 adi w rd, k add immediate to w ord rd rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 sbi w rd, k subtract immediate from w ord rd + 1:rd rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff - rd z,c,n,v,s 1 neg rd two?s complement rd $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd - 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 mul rd,rr multiply unsigned r1:r0 rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) z, eind none 2 jmp k jump pc k none 3 rcall k relative call subroutine pc pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) z, eind none 3 (1)
58 8068t?avr?12/10 xmega a3 call k call subroutine pc k none 3 / 4 (1) ret subroutine return pc stack none 4 / 5 (1) reti interrupt return pc stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd rr none 1 mov w rd, rr copy register pair rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 lds rd, k load direct from data space rd (k) none 2 (1)(2) ld rd, x load indirect rd (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x x - 1, rd (x) x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd (y) (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y (y) y + 1 none 1 (1)(2) mnemonics operands description operation flags #clocks
59 8068t?avr?12/10 xmega a3 ld rd, -y load indirect and pre-decrement y rd y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd (y + q) none 2 (1)(2) ld rd, z load indirect rd (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) rd none 2 (1) st x, rr store indirect (x) rr none 1 (1) st x+, rr store indirect and post-increment (x) x rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) x - 1, rr none 2 (1) st y, rr store indirect (y) rr none 1 (1) st y+, rr store indirect and post-increment (y) y rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) rr none 2 (1) st z, rr store indirect (z) rr none 1 (1) st z+, rr store indirect and post-increment (z) z rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) rr none 2 (1) lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-increment rd z (z), z + 1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z (rampz:z), z + 1 none 3 spm store program memory (rampz:z) r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z r1:r0, z + 2 none - in rd, a in from i/o location rd i/o(a) none 1 out a, rr out to i/o location i/o(a) rr none 1 push rr push register on stack stack rr none 1 (1) pop rd pop register from stack rd stack none 2 (1) bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c rd(n+1), 0, rd(0) z,c,n,v 1 mnemonics operands description operation flags #clocks
60 8068t?avr?12/10 xmega a3 notes: 1. cycle times for data memo ry accesses assume internal memo ry accesses, and are not valid for accesses via the external ram interface. 2. one extra cycle must be added when accessing internal sram. rol rd rotate left through carry rd(0) rd(n+1) c c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 s w ap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0sreg(s)1 sbi a, b set bit in i/o register i/o(a, b) 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) 0 none 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0h1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 w dr w atchdog reset (see specific descr. for w dr) none 1 mnemonics operands description operation flags #clocks
61 8068t?avr?12/10 xmega a3 33. packaging information 33.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
62 8068t?avr?12/10 xmega a3 33.2 64m2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m2 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, e 64m2 2010-10-20 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 7.50 7.65 7.80 8.90 9.00 9.10 8.90 9.00 9.10 e e2 7.50 7.65 7.80 e 0.50 bsc l 0.35 0.40 0.45 top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 0.20 0.27 0.40 2. dimension and tolerance conform to asmey14.5m-1994. 0.20 ref a3 a3 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k notes: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 7.65 mm exposed pad, micro lead frame package (mlf)
63 8068t?avr?12/10 xmega a3 34. electrical characteristics all typical values are measured at t = 25 c unless other temperature condition is given. all min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 34.1 absolute maximum ratings* 34.2 dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground..-0.5v to v cc +0.5v maximum operating voltage ............................................ 3.6v dc current per i/o pin ............................................... 20.0 ma dc current v cc and gnd pins................................ 200.0 ma table 34-1. current consumption symbol parameter condition min typ max units i cc power supply current (1) active 32 khz, ext. clk v cc = 1.8v 25 a v cc = 3.0v 71 1 mhz, ext. clk v cc = 1.8v 317 v cc = 3.0v 697 2 mhz, ext. clk v cc = 1.8v 613 800 v cc = 3.0v 1340 1800 32 mhz, ext. clk v cc = 3.0v 15.7 18 ma idle 32 khz, ext. clk v cc = 1.8v 3.6 a v cc = 3.0v 6.9 1 mhz, ext. clk v cc = 1.8v 112 v cc = 3.0v 215 2 mhz, ext. clk v cc = 1.8v 224 350 v cc = 3.0v 430 650 32 mhz, ext. clk v cc = 3.0v 6.9 8 ma power-down mode all functions disabled, t = 25c v cc = 3.0v 0.1 3 a all functions disabled, t = 85c v cc = 3.0v 1.75 5 ulp, w dt, sampled bod, t = 25c v cc = 1.8v 1 6 v cc = 3.0v 1 6 ulp, w dt, sampled bod, t=85c v cc = 3.0v 2.7 10
64 8068t?avr?12/10 xmega a3 note: 1. all power reduction registers set. 2. all parameters measured as the difference in current co nsumption between module enabled and disabled. all data at v cc =3.0v, clk sys = 1 mhz external cloc k with no prescaling. i cc power-save mode rtc 1 khz from low power 32 khz tosc, t = 25c v cc = 1.8v 0.5 4 a v cc = 3.0v 0.7 4 rtc from low power 32 khz tosc v cc = 3.0v 1.16 reset current consumption without reset pull-up resistor current v cc = 3.0v 1300 module current consumption (2) i cc rc32m 460 a rc32m w/dfll internal 32.768 khz oscillator as dfll source 594 rc2m 101 rc2m w/dfll internal 32.768 khz oscillator as dfll source 134 rc32k 27 pll multiplication factor = 10x 202 w atchdog normal mode 1 bod continuous mode 128 bod sampled mode 1 internal 1.00 v ref 80 temperature reference 74 rtc with int. 32 khz rc as source no prescaling 27 rtc with ulp as source no prescaling 1 adc 250 ks/s - int. 1v ref 2.9 ma dac normal mode 1000 ks/s, single channel, int. 1v ref 1.8 dac low-power mode 1000 ks/s, single channel, int. 1v ref 0.95 dac s/h normal mode int.1.1v ref, refresh 16clk 2.9 dac low-power mode s/h int. 1.1v ref, refresh 16clk 1.1 ac high-speed 195 a ac low-power 103 usart rx and tx enabled, 9600 baud 5.4 dma 128 timer/counter prescaler div1 20 aes 223 flash/eeprom programming vcc = 2v 25 ma vcc = 3v 33 table 34-1. current consumption (continued) symbol parameter condition min typ max units
65 8068t?avr?12/10 xmega a3 34.3 operating volt age and frequency the maximum cpu clock frequency of the xmega a3 devices is depending on v cc . as shown in figure 34-1 on page 65 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 34-1. maximum frequency vs. vcc table 34-2. operating voltage and frequency symbol parameter condition min typ max units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32 1. 8 12 32 mhz v 2.7 3.6 1.6 safe operating area
66 8068t?avr?12/10 xmega a3 34.4 flash and eeprom memory characteristics notes: 1. programming is timed from the internal 2 mhz oscillator. 2. eeprom is not erased if the eesave fuse is programmed. table 34-3. endurance and data retention symbol parameter condi tion min typ max units flash w rite/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom w rite/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 table 34-4. programming time symbol parameter condition min typ (1) max units chip erase flash, eeprom (2) and sram erase 40 ms flash page erase 6 page w rite 6 page w riteautomatic page erase and w rite 12 eeprom page erase 6 page w rite 6 page w riteautomatic page erase and w rite 12
67 8068t?avr?12/10 xmega a3 34.5 adc characteristics note: 1. refer to ?bandgap characteristics? on page 68 for more parameter details. table 34-5. adc characteristics symbol parameter condition min typ max units res resolution programmable: 8/12 8 12 12 bits inl integral non-linearity differential mode, 500ksps -5 2 5 lsb dnl differential non-linearity differential mode, 500ksps < 1 lsb gain error < 10 mv offset error < 2 mv adc clk adc clock frequency max is 1/4 of peripheral clock 2000 khz conversion rate 2000 ksps conversion time (propagation delay) (res+2)/2+gain res = 8 or 12, gain = 0, 1, 2 or 3 578 adc clk cycles sampling time 1/2 adc clk cycle 0.25 us conversion range 0 vref v avcc analog supply voltage v cc -0.3 v cc +0.3 v vref reference voltage 1.0 v cc -0.6 v input bandwidth khz int1v internal 1.00v reference (1) 1.00 v intvcc internal v cc /1.6 v cc /1.6 v scaledvcc scaled internal v cc /10 input v cc /10 v r aref reference input resistance > 10 m start-up time 12 24 adc clk cycles internal input sampling speed temp. sensor, v cc /10, bandgap 100 ksps table 34-6. adc gain stage characteristics symbol parameter condition min typ max units gain error 1 to 64 gain < 1 % offset error < 1 mv vrms noise level at input 64x gain vref = int. 1v 0.12 vref = ext. 2v 0.06 clock rate same as adc 1000 khz
68 8068t?avr?12/10 xmega a3 34.6 dac characteristics 34.7 analog comparator characteristics 34.8 bandgap characteristics table 34-7. dac characteristics symbol parameter condi tion min typ max units inl integral non-linearity v cc = 1.6-3.6v vref = ext. ref 5 lsb dnl differential non-linearity v cc = 1.6-3.6v vref = ext. ref <1 vref= av cc f clk conversion rate 1000 ksps aref external reference voltage 1.1 av cc -0.6 v reference input impedance >10 m max output voltage r load =100k av cc *0.98 v min output voltage r load =100k 0.015 offset factory calibration accuracy continues mode, v cc =3.0v, vref = int 1.00v, t=85c 0.5 lsb gain factory calibration accuracy 2.5 table 34-8. analog comparator characteristics symbol parameter condition min typ max units v off input offset voltage v cc = 1.6 - 3.6v <10 mv i lk input leakage current v cc = 1.6 - 3.6v < 1000 pa v hys1 hysteresis, no v cc = 1.6 - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6 - 3.6v mode = hs 20 v hys3 hysteresis, large v cc = 1.6 - 3.6v mode = hs 40 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 100 ns v cc = 1.6 - 3.6v mode = hs 110 v cc = 1.6 - 3.6v mode = lp 175 table 34-9. bandgap voltage characteristics symbol parameter condition min typ max units bandgap startup time as reference for adc or dac 1 clk_per + 2.5s s as input to ac or adc 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1 1.01 variation over voltage and temperature v cc = 1.6 - 3.6v, t = -40 c to 85 c2 %
69 8068t?avr?12/10 xmega a3 34.9 brownout detection characteristics note: 1. bod is calibrated at 85c within bod leve l 0 values, and bod level 0 is the default level. 34.10 pad characteristics table 34-10. brownout detection characteristics (1) symbol parameter condition min typ max units bod level 0 falling vcc 1.62 1.63 1.7 v bod level 1 falling vcc 1.9 bod level 2 falling vcc 2.17 bod level 3 falling vcc 2.43 bod level 4 falling vcc 2.68 bod level 5 falling vcc 2.96 bod level 6 falling vcc 3.22 bod level 7 falling vcc 3.49 hysteresis bod level 0-5 1 % table 34-11. pad characteristics symbol parameter condition min typ max units v ih input high voltage v cc = 2.4 - 3.6v 0.7*v cc v cc +0.5 v v cc = 1.6 - 2.4v 0.8*v cc v cc +0.5 v il input low voltage v cc = 2.4 - 3.6v -0.5 0.3*v cc v cc = 1.6 - 2.4v -0.5 0.2*v cc v ol output low voltage gpio i oh = 15 ma, v cc = 3.3v 0.4 0.76 i oh = 10 ma, v cc = 3.0v 0.3 0.64 i oh = 5 ma, v cc = 1.8v 0.2 0.46 v oh output high voltage gpio i oh = -8 ma, v cc = 3.3v 2.6 2.9 i oh = -6 ma, v cc = 3.0v 2.1 2.7 i oh = -2 ma, v cc = 1.8v 1.4 1.6 i il input leakage current i/o pin <0.001 1 a i ih input leakage current i/o pin <0.001 1 r p i/o pin pull/buss keeper resistor 20 k r rst reset pin pull-up resistor 20 input hysteresis 0.5 v
70 8068t?avr?12/10 xmega a3 34.11 por characteristics 34.12 reset characteristics 34.13 oscillator characteristics table 34-12. power-on reset characteristics symbol parameter condition min typ max units v pot- por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 0.8 v cc falls at 1v/ms or slower 0.8 1.3 v v pot+ por threshold voltage rising v cc 1.3 1.59 table 34-13. reset characteristics symbol parameter condi tion min typ max units minimum reset pulse width 90 1000 ns reset threshold voltage v cc = 2.7 - 3.6v 0.45*v cc v v cc = 1.6 - 2.7v 0.42*v cc table 34-14. internal 32.768 khz os cillator characteristics symbol parameter condi tion min typ max units accuracy t = 85 c, v cc = 3v, after production calibration -0.5 0.5 % table 34-15. internal 2 mhz oscilla tor characteristics symbol parameter condi tion min typ max units accuracy t = 85 c, v cc = 3v, after production calibration -1.5 1.5 % dfll calibration step size t = 25 c, v cc = 3v 0.15 table 34-16. internal 32 mhz oscillator characteristics symbol parameter condi tion min typ max units accuracy t = 85 c, v cc = 3v, after production calibration -1.5 1.5 % dfll calibration stepsize t = 25 c, v cc = 3v 0.2 table 34-17. internal 32 khz, ulp o scillator characteristics symbol parameter condition min typ max units output frequency 32 khz ulp osc t = 85 c, v cc = 3.0v 26 khz
71 8068t?avr?12/10 xmega a3 note: 1. see figure 34-2 on page 71 for definition figure 34-2. tosc input capacitance the input capacitance between the tosc pins is cl1 + cl2 in series as seen from the crystal when oscillating without external capacitors. notes: 1. non-prescaled system clock source. 2. time from pin change on external interrupt pin to first available clock cycle. additi onal interrupt respon se time is minimum 5 system clock source cycles. table 34-18. external 32.768khz crystal osc illator and tosc characteristics symbol parameter condi tion min typ max units sf safety factor capacitive load matched to crystal specification 3 esr/r 1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k crystal load capacitance 9.0pf 35 c in_tosc input capacitance between tosc pins normal mode 1.7 pf low power mode 2.2 c l1 c l2 tosc1 tosc2 device internal external 32.768 khz crystal table 34-19. device wake-up time from sleep symbol parameter condition (1) min typ (2) max units idle sleep, standby and extended standby sleep mode int. 32.768 khz rc 130 s int. 2 mhz rc 2 ext. 2 mhz clock 2 int. 32 mhz rc 0.17 power-save and power-down sleep mode int. 32.768 khz rc 320 int. 2 mhz rc 10.3 ext. 2 mhz clock 4.5 int. 32 mhz rc 5.8
72 8068t?avr?12/10 xmega a3 35. typical characteristics 35.1 active supply current figure 35-1. active supply current vs. frequency f sys = 0 - 1.0 mhz external clock, t = 25c figure 35-2. active supply current vs. frequency f sys = 1 - 32 mhz external clock, t = 25c 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 100 200 300 400 500 600 700 8 00 900 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ u a] 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 14 16 1 8 20 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] i cc [ma] 2.2 v 1. 8 v
73 8068t?avr?12/10 xmega a3 figure 35-3. active supply current vs. vcc f sys = 1.0 mhz external clock figure 35-4. active supply current vs. vcc f sys = 32.768 khz internal rc 8 5 c 25 c -40 c 0 100 200 300 400 500 600 700 8 00 900 1000 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a] 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a]
74 8068t?avr?12/10 xmega a3 figure 35-5. active supply current vs. vcc f sys = 2.0 mhz internal rc figure 35-6. active supply current vs. vcc f sys = 32 mhz internal rc prescaled to 8 mhz 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 2000 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a] 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ma]
75 8068t?avr?12/10 xmega a3 figure 35-7. active supply current vs. vcc f sys = 32 mhz internal rc 35.2 idle supply current figure 35-8. idle supply current vs. frequency f sys = 0 - 1.0 mhz, t = 25c 8 5 c 25 c -40 c 0 5 10 15 20 25 2.7 2. 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [ v ] i cc [ma] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 50 100 150 200 250 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ u a]
76 8068t?avr?12/10 xmega a3 figure 35-9. idle supply current vs. frequency f sys = 1 - 32 mhz, t = 25c figure 35-10. idle supply current vs. vcc f sys = 1.0 mhz external clock 3.3 v 3.0 v 2.7 v 0 1 2 3 4 5 6 7 8 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] i cc [ma] 1. 8 v 2.2 v 8 5 c 25 c -40 c 0 50 100 150 200 250 300 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a]
77 8068t?avr?12/10 xmega a3 figure 35-11. idle supply current vs. vcc f sys = 32.768 khz internal rc figure 35-12. idle supply current vs. vcc f sys = 2.0 mhz internal rc 8 5 c 25 c -40 c 0 5 10 15 20 25 30 35 40 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a] 8 5 c 25 c -40 c 0 100 200 300 400 500 600 700 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a]
78 8068t?avr?12/10 xmega a3 figure 35-13. idle supply current vs. vcc f sys = 32 mhz internal rc prescaled to 8 mhz figure 35-14. idle supply current vs. vcc f sys = 32 mhz internal rc 8 5 c 25 c -40 c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0 2 4 6 8 10 2.7 2. 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [ v ] i cc [ma]
79 8068t?avr?12/10 xmega a3 35.3 power-down supply current figure 35-15. power-down supply current vs. temperature figure 35-16. power-down supply current vs. temperature with wdt and sampled bod enabled. 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] i cc [ u a] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] i cc [ u a]
80 8068t?avr?12/10 xmega a3 35.4 power-save supply current figure 35-17. power-save supply current vs. temperature with wdt, sampled bod and rtc from ulp enabled 35.5 pin pull-up figure 35-18. reset pull-up resistor curr ent vs. reset pin voltage v cc = 1.8v 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] i cc [ u a] 8 5 c 25 c -40 c 0 20 40 60 8 0 100 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset [ v ] i reset [ u a]
81 8068t?avr?12/10 xmega a3 figure 35-19. reset pull-up resistor curr ent vs. reset pin voltage v cc = 3.0v figure 35-20. reset pull-up resistor curr ent vs. reset pin voltage v cc = 3.3v 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 0 0.5 1 1.5 2 2.5 3 v reset [ v ] i reset [ u a] 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1 8 0 0 0.5 1 1.5 2 2.5 3 v reset [ v ] i reset [ u a]
82 8068t?avr?12/10 xmega a3 35.6 pin output voltage vs. sink/source current figure 35-21. i/o pin output voltage vs. source current vcc = 1.8v figure 35-22. i/o pin output voltage vs. source current vcc = 3.0v 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 -12 -10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ] 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ]
83 8068t?avr?12/10 xmega a3 figure 35-23. i/o pin output voltage vs. source current vcc = 3.3v figure 35-24. i/o pin output voltage vs. sink current vcc = 1.8v 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ] -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ] 25c 8 5c
84 8068t?avr?12/10 xmega a3 figure 35-25. i/o pin output voltage vs. sink current vcc = 3.0v figure 35-26. i/o pin output voltage vs. sink current vcc = 3.3v 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ] 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ]
85 8068t?avr?12/10 xmega a3 35.7 pin thresholds and hysteresis figure 35-27. i/o pin input threshold voltage vs. v cc v ih - i/o pin read as ?1? figure 35-28. i/o pin input threshold voltage vs. v cc v il - i/o pin read as ?0? 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ] 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ]
86 8068t?avr?12/10 xmega a3 figure 35-29. i/o pin input hysteresis vs. v cc figure 35-30. reset input threshold voltage vs. v cc v ih - i/o pin read as ?1? 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ] 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ]
87 8068t?avr?12/10 xmega a3 figure 35-31. reset input threshold voltage vs. v cc v il - i/o pin read as ?0? 35.8 bod thresholds figure 35-32. bod thresholds vs. temperature bod level = 1.6v 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ] rising v cc falling v cc 1.61 1.62 1.63 1.64 1.65 1.66 1.67 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] v bot [ v ]
88 8068t?avr?12/10 xmega a3 figure 35-33. bod thresholds vs. temperature bod level = 2.9v 35.9 oscillators and wake-up time 35.9.1 internal 32.768 khz oscillator figure 35-34. internal 32.768 khz oscilla tor calibration step size t = -40 to 85 c, v cc = 3v rising v cc falling v cc 2.9 2.92 2.94 2.96 2.9 8 3 3.02 3.04 3.06 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] v bot [ v ] 032649612 8 160 192 224 256 rc32kcal[7..0] 0.05 % 0.20 % 0.35 % 0.50 % 0.65 % 0. 8 0 % step size: f [khz]
89 8068t?avr?12/10 xmega a3 35.9.2 internal 2 mhz oscillator figure 35-35. internal 2 mhz oscillator ca la calibration step size t = -40 to 85 c, v cc = 3v figure 35-36. internal 2 mhz oscillator ca lb calibration step size t = -40 to 85 c, v cc = 3v -0.30 % -0.20 % -0.10 % 0.00 % 0.10 % 0.20 % 0.30 % 0.40 % 0.50 % 016324 8 64 8 09611212 8 dfllrc2mcala step size: f [mhz] 0.00 % 0.50 % 1.00 % 1.50 % 2.00 % 2.50 % 3.00 % 0 8 16 24 32 40 4 8 56 64 dfllrc2mcalb step size: f [mhz]
90 8068t?avr?12/10 xmega a3 35.9.3 internal 32 mhz oscillator figure 35-37. internal 32 mhz oscillator cala calibration step size t = -40 to 85 c, v cc = 3v figure 35-38. internal 32 mhz oscillator calb calibration step size t = -40 to 85 c, v cc = 3v -0.20 % -0.10 % 0.00 % 0.10 % 0.20 % 0.30 % 0.40 % 0.50 % 0.60 % 016324 8 64 8 0 96 112 12 8 dfllrc32mcala step size: f [mhz] 0.00 % 0.50 % 1.00 % 1.50 % 2.00 % 2.50 % 3.00 % 0 8 16 24 32 40 4 8 56 64 dfllrc32mcalb step size: f [mhz]
91 8068t?avr?12/10 xmega a3 35.10 module current consumption figure 35-39. ac current consumption vs. vcc low-power mode figure 35-40. power-up current consumption vs. vcc 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] mod u le c u rrent cons u mption [ u a] 8 5 c 25 c -40 c 0 100 200 300 400 500 600 700 0.4 0.6 0. 8 1 1.2 1.4 1.6 v cc [ v ] i cc [ u a]
92 8068t?avr?12/10 xmega a3 35.11 reset pulsewidth figure 35-41. minimum reset pulse w idth vs. vcc 35.12 pdi speed figure 35-42. pdi speed vs. vcc 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] t rst [ns] 25 c 0 5 10 15 20 25 30 35 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] f max [mhz]
93 8068t?avr?12/10 xmega a3 36. errata 36.1 atxmega256a3 36.1.1 rev. e ? bandgap voltage input for the acs can not be ch anged when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4 v ? adc event on compare match non-functional ? bandgap measurement with the adc is no n-functional when vcc is below 2.7v ? accuracy lost on first th ree samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega a manual ? pwm is not restarted properly afte r a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? dac is nonlinear and inaccurate when re ference is above 2.4v or vcc - 0.6v ? dac has increased inl or noise for some operating conditions ? dac refresh may be blocked in s/h mode ? conversion lost on dac channel b in event triggered mode ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not aff ect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? crystal start-up time required after powe r-save even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag no t cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one analog comparator (ac) and then selected/deselected as input for another ac, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear.
94 8068t?avr?12/10 xmega a3 figure 36-1. analog comparator voltage scaler vs. scalefac t = 25c problem fix/workaround use external voltage input for the analog comparator if accurate voltage levels are needed 3. adc has increased inl error for some operating conditions some adc configurations or operating co ndition will result in increased inl error. in signed mode inl is increased to: ? 6lsb for sample rates above 1msps, and up to 8 lsb for 2msps sample rate. ? 6lsb for reference voltage below 1.1v when vcc is above 3.0v. ? 20lsb for ambient temperature below 0 degree c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be guaranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 4. adc gain stage output range is limited to 2.4 v the amplified out put of the adc gain stage will never go above 2.4 v, hence the differential input will only give corr ect output when below 2.4 v/gain. for the ava ilable gain settings, this gives a differential input range of: ? 1x gain: 2.4 v ? 2x gain: 1.2 v ? 4x gain: 0.6 v ? 8x gain: 300 mv ? 16x gain: 150 mv ? 32x gain: 75 mv ? 64x gain: 38 mv 3.3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [ v ]
95 8068t?avr?12/10 xmega a3 problem fix/workaround keep the amplified voltage output from the adc gain stage below 2.4 v in order to get a cor- rect result, or keep adc voltage reference below 2.4 v. 5. adc event on compare match non-functional adc signalling event will be given at every conversion complete even if interr upt mode (int- mode) is set to belo w or above. problem fix/workaround enable and use interrupt on compare match when using the compare function. 6. bandgap measurement with the adc is non-functional when vcc is below 2.7v the adc can not be used to do bandgap measurements when vcc is below 2.7v. problem fix/workaround none. 7. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these results after changing input channels to adc gain stage. 8. configuration of pgm and cwcm not as described in xmega a manual enabling common w aveform channel mode will enable pattern generation mode (pgm), but not common w aveform channel mode. enabling pattern generation mode (pgm) and not common w aveform channel mode (c w cm) will enable both pattern ge neration mode and common w aveform channel mode. problem fix/workaround 9. pwm is not restarted properly after a fault in cycle-by-cycle mode w hen the a w ex fault restore mode is set to cycle- by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any a w ex i/o register to re-enable the output. 10. bod will be enabled after any reset if any reset source go es active, the bod will be enabled and keep the device in reset if the vcc voltage is below the prog rammed bod level. during powe r-on reset, reset will not be released until vcc is above the programmed bod level even if the bod is disabled. table 36-1. configure p w m and c w cm according to this table: pgm cwcm description 0 0 pgm and c w cm disabled 0 1 pgm enabled 1 0 pgm and c w cm enabled 1 1 pgm enabled
96 8068t?avr?12/10 xmega a3 problem fix/workaround do not set the bod level higher than vcc even if the bod is not used. 11. dac is nonlinear and inaccurate when reference is above 2.4v or vcc - 0.6v using the dac with a referenc e voltage above 2.4v or vcc - 0.6v will give inaccurate out- put when converting codes that give below 0.75v output: ? 10 lsb for continuous mode ? 200 lsb for sample and hold mode problem fix/workaround none. 12. dac has increased inl or noise for some operating conditions some dac configurations or operating cond ition will result in increased output error. ? continous mode: 5 lsb ? sample and hold mode: 15 lsb ? sample and hold mode for reference above 2.0v: up to 100 lsb problem fix/workaround none. 13. dac refresh may be blocked in s/h mode if the dac is running in sample and hold (s/h) mode and conversion for one channel is done at maximum rate (i.e. the dac is always busy doing conversion fo r this channel), this will block refresh signals to the second channel. problem fix/workaround w hen using the dac in s/h mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. conversion lost on dac channel b in event triggered mode if during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. this means that not all data-values written to the channel 1 data register are converted. problem fix/workaround keep the dac conversion interval in the range 000-001 (1 and 3 clk), and limit the periph- eral clock frequency so the conversion internal never is shorter than 1.5 s. 15. eeprom page buffer always written when nvm data0 is written if the eeprom is memory mapp ed, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data0, for exampl e when doing software crc or flash page buffer write, check if eeprom page buff er active loading flag (eeloa d) is set. do not write nvm data0 when eeload is set.
97 8068t?avr?12/10 xmega a3 16. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignor ed until the device is woken from another source or the source triggers again. this applies w hen entering all sleep modes where the system clock is stopped. problem fix/workaround none. 17. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (i.e. connect positive input to the negative ac input and vice versa), or use and external inverter to change polarity of analog comparator output. 18. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failure (xoscf dif) will be automatically cleared when exe- cuting the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt source in software is not required. 19. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768 khz crystal is used for rtc duri ng sleep, the clock fr om the crystal will not be ready for the system before th e specified start-up time. see "xoscsel[3:0]: crystal oscilla- tor selection" in xmega a manual. if bod is us ed in active mode, the bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required , go to sleep with internal oscillator as system clock. 20. rtc counter value not correctly read after sleep if the rtc is set to wake up the device on rt c overflow and bit 0 of rtc cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle after wakeup. the value read will be the same as the value in the register when entering sleep. the same applies if rtc compare match is used as wake-up source. problem fix/workaround w ait at least one prescaled rtc clock cycle before reading the rtc cnt value. 21. pending asynchronous rtc-inte rrupts will not wa ke up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none.
98 8068t?avr?12/10 xmega a3 22. twi transmit collision flag not cleared on repeated start the t w i transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 23. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peripheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be low before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 24. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on the same peripheral clock cycle as a start is detected, the tr ansaction will be dropped. problem fix/workaround none. 25. twi data interrupt flag erroneously read as set w hen issuing the t w i slave response command cmd=0b11, it takes 1 peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif.
99 8068t?avr?12/10 xmega a3 26. wdr instruction inside closed window will not issue reset w hen a w dr instruction is execute within one ulp clock cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround w ait at least one ulp clock cycle before executing a w dr instruction.
100 8068t?avr?12/10 xmega a3 36.1.2 rev. b ? bandgap voltage input for the acs can not be ch anged when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4 v ? adc event on compare match non-functional ? bandgap measurement with the adc is no n-functional when vcc is below 2.7v ? accuracy lost on first th ree samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega a manual ? pwm is not restarted properly afte r a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? dac is nonlinear and inaccurate when re ference is above 2.4v or vcc - 0.6v ? dac has increased inl or noise for some operating conditions ? dac refresh may be blocked in s/h mode ? conversion lost on dac channel b in event triggered mode ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not aff ect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after powe r-save even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag no t cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one analog comparator (ac) and then selected/deselected as input for another ac, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear.
101 8068t?avr?12/10 xmega a3 figure 36-2. analog comparator voltage scaler vs. scalefac t = 25c problem fix/workaround use external voltage input for the analog comparator if accurate voltage levels are needed 3. adc has increased inl error for some operating conditions some adc configurations or operating co ndition will result in increased inl error. in signed mode inl is increased to: ? 6lsb for sample rates above 1msps, and up to 8lsb for 2msps sample rate. ? 6lsb for reference voltage below 1.1v when vcc is above 3.0v. ? 20lsb for ambient temperature below 0 degree c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be guaranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 4. adc gain stage output range is limited to 2.4 v the amplified out put of the adc gain stage will never go above 2.4 v, hence the differential input will only give corr ect output when below 2.4 v/gain. for the ava ilable gain settings, this gives a differential input range of: ? 1x gain: 2.4 v ? 2x gain: 1.2 v ? 4x gain: 0.6 v ? 8x gain: 300 mv ? 16x gain: 150 mv ? 32x gain: 75 mv ? 64x gain: 38 mv 3.3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [ v ]
102 8068t?avr?12/10 xmega a3 problem fix/workaround keep the amplified voltage output from the adc gain stage below 2.4 v in order to get a cor- rect result, or keep adc voltage reference below 2.4 v. 5. adc event on compare match non-functional adc signalling event will be given at every conversion complete even if interr upt mode (int- mode) is set to belo w or above. problem fix/workaround enable and use interrupt on compare match when using the compare function. 6. bandgap measurement with the adc is non-functional when vcc is below 2.7v the adc can not be used to do bandgap measurements when vcc is below 2.7v. problem fix/workaround none. 7. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these results after changing input channels to adc gain stage. 8. configuration of pgm and cwcm not as described in xmega a manual enabling common w aveform channel mode will enable pattern generation mode (pgm), but not common w aveform channel mode. enabling pattern generation mode (pgm) and not common w aveform channel mode (c w cm) will enable both pattern ge neration mode and common w aveform channel mode. problem fix/workaround 9. pwm is not restarted properly after a fault in cycle-by-cycle mode w hen the a w ex fault restore mode is set to cycle- by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any a w ex i/o register to re-enable the output. 10. bod will be enabled after any reset if any reset source go es active, the bod will be enabled and keep the device in reset if the vcc voltage is below the prog rammed bod level. during powe r-on reset, reset will not be released until vcc is above the programmed bod level even if the bod is disabled. table 36-2. configure p w m and c w cm according to this table: pgm cwcm description 0 0 pgm and c w cm disabled 0 1 pgm enabled 1 0 pgm and c w cm enabled 1 1 pgm enabled
103 8068t?avr?12/10 xmega a3 problem fix/workaround do not set the bod level higher than vcc even if the bod is not used. 11. dac is nonlinear and inaccurate when reference is above 2.4v or vcc - 0.6v using the dac with a referenc e voltage above 2.4v or vcc - 0.6v will give inaccurate out- put when converting codes that give below 0.75v output: ? 10 lsb for continuous mode ? 200 lsb for sample and hold mode problem fix/workaround none. 12. dac has increased inl or noise for some operating conditions some dac configurations or operating cond ition will result in increased output error. ? continous mode: 5 lsb ? sample and hold mode: 15 lsb ? sample and hold mode for reference above 2.0v: up to 100 lsb problem fix/workaround none. 13. dac refresh may be blocked in s/h mode if the dac is running in sample and hold (s/h) mode and conversion for one channel is done at maximum rate (i.e. the dac is always busy doing conversion fo r this channel), this will block refresh signals to the second channel. problem fix/workaround w hen using the dac in s/h mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. conversion lost on dac channel b in event triggered mode if during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. this means that not all data-values written to the channel 1 data register are converted. problem fix/workaround keep the dac conversion interval in the range 000-001 (1 and 3 clk), and limit the periph- eral clock frequency so the conversion internal never is shorter than 1.5 s. 15. eeprom page buffer always written when nvm data0 is written if the eeprom is memory mapp ed, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data0, for exampl e when doing software crc or flash page buffer write, check if eeprom page buff er active loading flag (eeloa d) is set. do not write nvm data0 when eeload is set.
104 8068t?avr?12/10 xmega a3 16. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignor ed until the device is woken from another source or the source triggers again. this applies w hen entering all sleep modes where the system clock is stopped. problem fix/workaround none. 17. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (i.e. connect positive input to the negative ac input and vice versa), or use and external inverter to change polarity of analog comparator output. 18. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failure (xoscf dif) will be automatically cleared when exe- cuting the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt source in software is not required. 19. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be written while reading eeprom or flash, or while exe- cuting code in active mode. problem fix/workaround enter idle sleep mode within 2.5 s (five 2 mh z clock cycles and 80 32 mhz clock cycles) after starting an eeprom or flash write operation. w ake-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic erase-and-write operation has started, and then enter idle sleep mode. 20. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768 khz crystal is used for rtc duri ng sleep, the clock fr om the crystal will not be ready for the system before th e specified start-up time. see "xoscsel[3:0]: crystal oscilla- tor selection" in xmega a manual. if bod is us ed in active mode, the bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required , go to sleep with internal oscillator as system clock. 21. rtc counter value not correctly read after sleep if the rtc is set to wake up the device on rt c overflow and bit 0 of rtc cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle after wakeup. the value read will be the same as the value in the register when entering sleep. the same applies if rtc compare match is used as wake-up source.
105 8068t?avr?12/10 xmega a3 problem fix/workaround w ait at least one prescaled rtc clock cycle before reading the rtc cnt value. 22. pending asynchronous rtc-inte rrupts will not wa ke up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 23. twi transmit collision flag not cleared on repeated start the t w i transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 24. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peripheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be low before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 25. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on the same peripheral clock cycle as a start is detected, the tr ansaction will be dropped.
106 8068t?avr?12/10 xmega a3 problem fix/workaround none. 26. twi data interrupt flag erroneously read as set w hen issuing the t w i slave response command cmd=0b11, it takes 1 peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 27. wdr instruction inside closed window will not issue reset w hen a w dr instruction is execute within one ulp clock cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround w ait at least one ulp clock cycle before executing a w dr instruction.
107 8068t?avr?12/10 xmega a3 36.1.3 rev. a ? bandgap voltage input for the acs cannot be ch anged when used for bo th acs simultaneously ? adc gain stage output range is limited to 2.4v ? sampled bod in active mode will cause no ise when bandgap is used as reference ? flash power reduction mode can not be enabled when entering sleep mode ? jtag enable does not override analog comparator b output ? bandgap measurement with the adc is non-functional when v cc is below 2.7v ? dac refresh may be blocked in s/h mode ? bod will be enabled after any reset ? both dflls and both oscillators has to be enabled for one to work ? operating frequency an d voltage limitations ? inverted i/o enable does not a ffect analog comparator outpu t 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one analog comparator (ac) and then selected/deselected as input fo r the another ac, the first com parator will be affected for up to 1 us and could potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously, configure the input selection for both acs before enabling any of them. 2. adc gain stage output range is limited to 2.4 v the amplified out put of the adc gain stage will never go above 2.4 v, hence the differential input will only give corr ect output when below 2.4 v/gain. for the ava ilable gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain stage below 2.4 v in order to get a cor- rect result, or keep adc voltage reference below 2.4 v. 3. sampled bod in active mode will cause noise when bandgap is used as reference using the bod in sample d mode when the device is runnin g in active or idle mode will add noise on the bandgap reference for adc, dac and analog comparator. problem fix/workaround if the bandgap is used as reference for either the adc, dac and analog comparator, the bod must not be set in sampled mode. ? 1x gain: 2.4 v ? 2x gain: 1.2 v ? 4x gain: 0.6 v ? 8x gain: 300 mv ? 16x gain: 150 mv ? 32x gain: 75 mv ? 64x gain: 38 mv
108 8068t?avr?12/10 xmega a3 4. flash power reduction mode can not be enabled when entering sleep mode if flash power reduction mode is enabled wh en a deep sleep mode, the device will only wake up on every fourth wake-up request. if flash power reduction mode is enabled when entering idle sleep mode, the wake-up time will vary with up to 16 cpu clock cycles. problem fix/workaround disable flash power reduction mode before entering sleep mode. 5. jtag enable does not override analog comparator b output w hen jtag is enabled this will not override the anlog comparator b (acb)ouput, ac0out on pin 7 if this is enabled. problem fix/workaround ac0out for acb should not be enabled when jt ag is used. use only analog comparator output for aca when jtag is used, or use the pdi as debug interface. 6. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc cannot be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround if internal voltages must be measured when v cc is below 2.7v, measure the internal 1.00v reference instead of the bandgap. 7. dac refresh may be blocked in s/h mode if the dac is running in sample and hold (s/h) mode and conversion for one channel is done at maximum rate (i.e. the dac is always busy doing conversion fo r this channel), this will block refresh signals to the second channel. problem fix/workarund w hen using the dac in s/h mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 8. bod will be enabled after any reset if any reset source go es active, the bod will be enabled and keep the device in reset if the vcc voltage is below the prog rammed bod level. during powe r-on reset, reset will not be released until vcc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than vcc even if the bod is not used. 9. both dflls and both oscillators has to be enabled for one to work in order to use the auto matic runtime calibration for the 2 mhz or the 32mhz internal oscilla- tors, the dfll for both oscillators and both os cillators has to be enabled for one to work. problem fix/workaround enable both the dflls and both oscillators when using automatic runtime calibration for one of the internal oscillators.
109 8068t?avr?12/10 xmega a3 10. operating frequency and voltage limitation to ensure correct operation, there is a limit on operating frequency and voltage. figure 36-3 on page 109 shows the safe operating area. figure 36-3. operating frequnecy and voltage limitation problem fix/workaround none, avoid using the device outside th ese frequnecy and voltage limitations. 11. inverted i/o enable does not affect analog comparator output the inverted i/o pin function does not affect the analog comparator output function. problem fix/workarund configure the analog comparator setup to give a inverted result (i.e. connect positive input to the negative ac input and vice versa), or use and externel inverter to change polarity of analog comparator output. mhz v 3.6 2.4 30 15 safe operating area
110 8068t?avr?12/10 xmega a3 36.2 atxmega192a3, a txmega128a3, atxmega64a3 36.2.1 rev. e ? bandgap voltage input for the acs can not be ch anged when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4 v ? adc event on compare match non-functional ? bandgap measurement with the adc is no n-functional when vcc is below 2.7v ? accuracy lost on first th ree samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega a manual ? pwm is not restarted properly afte r a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? dac is nonlinear and inaccurate when re ference is above 2.4v or vcc - 0.6v ? dac has increased inl or noise for some operating conditions ? dac refresh may be blocked in s/h mode ? conversion lost on dac channel b in event triggered mode ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not aff ect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? crystal start-up time required after powe r-save even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag no t cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one analog comparator (ac) and then selected/deselected as input for another ac, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear.
111 8068t?avr?12/10 xmega a3 figure 36-4. analog comparator voltage scaler vs. scalefac t = 25c problem fix/workaround use external voltage input for the analog comparator if accurate voltage levels are needed 3. adc has increased inl error for some operating conditions some adc configurations or operating co ndition will result in increased inl error. in signed mode inl is increased to: ? 6lsb for sample rates above 1msps, and up to 8 lsb for 2msps sample rate. ? 6lsb for reference voltage below 1.1v when vcc is above 3.0v. ? 20lsb for ambient temperature below 0 degree c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be guaranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 4. adc gain stage output range is limited to 2.4 v the amplified out put of the adc gain stage will never go above 2.4 v, hence the differential input will only give corr ect output when below 2.4 v/gain. for the ava ilable gain settings, this gives a differential input range of: ? 1x gain: 2.4 v ? 2x gain: 1.2 v ? 4x gain: 0.6 v ? 8x gain: 300 mv ? 16x gain: 150 mv ? 32x gain: 75 mv ? 64x gain: 38 mv 3.3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [ v ]
112 8068t?avr?12/10 xmega a3 problem fix/workaround keep the amplified voltage output from the adc gain stage below 2.4 v in order to get a cor- rect result, or keep adc voltage reference below 2.4 v. 5. adc event on compare match non-functional adc signalling event will be given at every conversion complete even if interr upt mode (int- mode) is set to belo w or above. problem fix/workaround enable and use interrupt on compare match when using the compare function. 6. bandgap measurement with the adc is non-functional when vcc is below 2.7v the adc can not be used to do bandgap measurements when vcc is below 2.7v. problem fix/workaround none. 7. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these results after changing input channels to adc gain stage. 8. configuration of pgm and cwcm not as described in xmega a manual enabling common w aveform channel mode will enable pattern generation mode (pgm), but not common w aveform channel mode. enabling pattern generation mode (pgm) and not common w aveform channel mode (c w cm) will enable both pattern ge neration mode and common w aveform channel mode. problem fix/workaround 9. pwm is not restarted properly after a fault in cycle-by-cycle mode w hen the a w ex fault restore mode is set to cycle- by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any a w ex i/o register to re-enable the output. 10. bod will be enabled after any reset if any reset source go es active, the bod will be enabled and keep the device in reset if the vcc voltage is below the prog rammed bod level. during powe r-on reset, reset will not be released until vcc is above the programmed bod level even if the bod is disabled. table 36-3. configure p w m and c w cm according to this table: pgm cwcm description 0 0 pgm and c w cm disabled 0 1 pgm enabled 1 0 pgm and c w cm enabled 1 1 pgm enabled
113 8068t?avr?12/10 xmega a3 problem fix/workaround do not set the bod level higher than vcc even if the bod is not used. 11. dac is nonlinear and inaccurate when reference is above 2.4v or vcc - 0.6v using the dac with a referenc e voltage above 2.4v or vcc - 0.6v will give inaccurate out- put when converting codes that give below 0.75v output: ? 10 lsb for continuous mode ? 200 lsb for sample and hold mode problem fix/workaround none. 12. dac has increased inl or noise for some operating conditions some dac configurations or operating cond ition will result in increased output error. ? continous mode: 5 lsb ? sample and hold mode: 15 lsb ? sample and hold mode for reference above 2.0v: up to 100 lsb problem fix/workaround none. 13. dac refresh may be blocked in s/h mode if the dac is running in sample and hold (s/h) mode and conversion for one channel is done at maximum rate (i.e. the dac is always busy doing conversion fo r this channel), this will block refresh signals to the second channel. problem fix/workaround w hen using the dac in s/h mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. conversion lost on dac channel b in event triggered mode if during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. this means that not all data-values written to the channel 1 data register are converted. problem fix/workaround keep the dac conversion interval in the range 000-001 (1 and 3 clk), and limit the periph- eral clock frequency so the conversion internal never is shorter than 1.5 s. 15. eeprom page buffer always written when nvm data0 is written if the eeprom is memory mapp ed, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data0, for exampl e when doing software crc or flash page buffer write, check if eeprom page buff er active loading flag (eeloa d) is set. do not write nvm data0 when eeload is set.
114 8068t?avr?12/10 xmega a3 16. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignor ed until the device is woken from another source or the source triggers again. this applies w hen entering all sleep modes where the system clock is stopped. problem fix/workaround none. 17. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (i.e. connect positive input to the negative ac input and vice versa), or use and external inverter to change polarity of analog comparator output. 18. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failure (xoscf dif) will be automatically cleared when exe- cuting the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt source in software is not required. 19. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768 khz crystal is used for rtc duri ng sleep, the clock fr om the crystal will not be ready for the system before th e specified start-up time. see "xoscsel[3:0]: crystal oscilla- tor selection" in xmega a manual. if bod is us ed in active mode, the bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required , go to sleep with internal oscillator as system clock. 20. rtc counter value not correctly read after sleep if the rtc is set to wake up the device on rt c overflow and bit 0 of rtc cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle after wakeup. the value read will be the same as the value in the register when entering sleep. the same applies if rtc compare match is used as wake-up source. problem fix/workaround w ait at least one prescaled rtc clock cycle before reading the rtc cnt value. 21. pending asynchronous rtc-inte rrupts will not wa ke up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none.
115 8068t?avr?12/10 xmega a3 22. twi transmit collision flag not cleared on repeated start the t w i transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 23. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peripheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be low before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 24. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on the same peripheral clock cycle as a start is detected, the tr ansaction will be dropped. problem fix/workaround none. 25. twi data interrupt flag erroneously read as set w hen issuing the t w i slave response command cmd=0b11, it takes 1 peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif.
116 8068t?avr?12/10 xmega a3 26. wdr instruction inside closed window will not issue reset w hen a w dr instruction is execute within one ulp clock cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround w ait at least one ulp clock cycle before executing a w dr instruction.
117 8068t?avr?12/10 xmega a3 36.2.2 rev. b ? bandgap voltage input for the acs can not be ch anged when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4 v ? adc event on compare match non-functional ? bandgap measurement with the adc is no n-functional when vcc is below 2.7v ? accuracy lost on first th ree samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega a manual ? pwm is not restarted properly afte r a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? dac is nonlinear and inaccurate when re ference is above 2.4v or vcc - 0.6v ? dac has increased inl or noise for some operating conditions ? dac refresh may be blocked in s/h mode ? conversion lost on dac channel b in event triggered mode ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not aff ect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after powe r-save even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag no t cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one analog comparator (ac) and then selected/deselected as input for another ac, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear.
118 8068t?avr?12/10 xmega a3 figure 36-5. analog comparator voltage scaler vs. scalefac t = 25c problem fix/workaround use external voltage input for the analog comparator if accurate voltage levels are needed 3. adc has increased inl error for some operating conditions some adc configurations or operating co ndition will result in increased inl error. in signed mode inl is increased to: ? 6lsb for sample rates above 1msps, and up to 8 lsb for 2msps sample rate. ? 6lsb for reference voltage below 1.1v when vcc is above 3.0v. ? 20lsb for ambient temperature below 0 degree c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be guaranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 4. adc gain stage output range is limited to 2.4 v the amplified out put of the adc gain stage will never go above 2.4 v, hence the differential input will only give corr ect output when below 2.4 v/gain. for the ava ilable gain settings, this gives a differential input range of: ? 1x gain: 2.4 v ? 2x gain: 1.2 v ? 4x gain: 0.6 v ? 8x gain: 300 mv ? 16x gain: 150 mv ? 32x gain: 75 mv ? 64x gain: 38 mv 3.3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [ v ]
119 8068t?avr?12/10 xmega a3 problem fix/workaround keep the amplified voltage output from the adc gain stage below 2.4 v in order to get a cor- rect result, or keep adc voltage reference below 2.4 v. 5. adc event on compare match non-functional adc signalling event will be given at every conversion complete even if interr upt mode (int- mode) is set to belo w or above. problem fix/workaround enable and use interrupt on compare match when using the compare function. 6. bandgap measurement with the adc is non-functional when vcc is below 2.7v the adc can not be used to do bandgap measurements when vcc is below 2.7v. problem fix/workaround none. 7. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these results after changing input channels to adc gain stage. 8. configuration of pgm and cwcm not as described in xmega a manual enabling common w aveform channel mode will enable pattern generation mode (pgm), but not common w aveform channel mode. enabling pattern generation mode (pgm) and not common w aveform channel mode (c w cm) will enable both pattern ge neration mode and common w aveform channel mode. problem fix/workaround 9. pwm is not restarted properly after a fault in cycle-by-cycle mode w hen the a w ex fault restore mode is set to cycle- by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any a w ex i/o register to re-enable the output. 10. bod will be enabled after any reset if any reset source go es active, the bod will be enabled and keep the device in reset if the vcc voltage is below the prog rammed bod level. during powe r-on reset, reset will not be released until vcc is above the programmed bod level even if the bod is disabled. table 36-4. configure p w m and c w cm according to this table: pgm cwcm description 0 0 pgm and c w cm disabled 0 1 pgm enabled 1 0 pgm and c w cm enabled 1 1 pgm enabled
120 8068t?avr?12/10 xmega a3 problem fix/workaround do not set the bod level higher than vcc even if the bod is not used. 11. dac is nonlinear and inaccurate when reference is above 2.4v or vcc - 0.6v using the dac with a referenc e voltage above 2.4v or vcc - 0.6v will give inaccurate out- put when converting codes that give below 0.75v output: ? 10 lsb for continuous mode ? 200 lsb for sample and hold mode problem fix/workaround none. 12. dac has increased inl or noise for some operating conditions some dac configurations or operating cond ition will result in increased output error. ? continous mode: 5 lsb ? sample and hold mode: 15 lsb ? sample and hold mode for reference above 2.0v: up to 100 lsb problem fix/workaround none. 13. dac refresh may be blocked in s/h mode if the dac is running in sample and hold (s/h) mode and conversion for one channel is done at maximum rate (i.e. the dac is always busy doing conversion fo r this channel), this will block refresh signals to the second channel. problem fix/workaround w hen using the dac in s/h mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. conversion lost on dac channel b in event triggered mode if during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. this means that not all data-values written to the channel 1 data register are converted. problem fix/workaround keep the dac conversion interval in the range 000-001 (1 and 3 clk), and limit the periph- eral clock frequency so the conversion internal never is shorter than 1.5 s. 15. eeprom page buffer always written when nvm data0 is written if the eeprom is memory mapp ed, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data0, for exampl e when doing software crc or flash page buffer write, check if eeprom page buff er active loading flag (eeloa d) is set. do not write nvm data0 when eeload is set.
121 8068t?avr?12/10 xmega a3 16. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignor ed until the device is woken from another source or the source triggers again. this applies w hen entering all sleep modes where the system clock is stopped. problem fix/workaround none. 17. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (i.e. connect positive input to the negative ac input and vice versa), or use and external inverter to change polarity of analog comparator output. 18. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failure (xoscf dif) will be automatically cleared when exe- cuting the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt source in software is not required. 19. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be written while reading eeprom or flash, or while exe- cuting code in active mode. problem fix/workaround enter idle sleep mode within 2.5 s (five 2 mh z clock cycles and 80 32 mhz clock cycles) after starting an eeprom or flash write operation. w ake-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic erase-and-write operation has started, and then enter idle sleep mode. 20. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768 khz crystal is used for rtc duri ng sleep, the clock fr om the crystal will not be ready for the system before th e specified start-up time. see "xoscsel[3:0]: crystal oscilla- tor selection" in xmega a manual. if bod is us ed in active mode, the bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required , go to sleep with internal oscillator as system clock. 21. rtc counter value not correctly read after sleep if the rtc is set to wake up the device on rt c overflow and bit 0 of rtc cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle after wakeup. the value read will be the same as the value in the register when entering sleep. the same applies if rtc compare match is used as wake-up source.
122 8068t?avr?12/10 xmega a3 problem fix/workaround w ait at least one prescaled rtc clock cycle before reading the rtc cnt value. 22. pending asynchronous rtc-inte rrupts will not wa ke up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 23. twi transmit collision flag not cleared on repeated start the t w i transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 24. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peripheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be low before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 25. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on the same peripheral clock cycle as a start is detected, the tr ansaction will be dropped.
123 8068t?avr?12/10 xmega a3 problem fix/workaround none. 26. twi data interrupt flag erroneously read as set w hen issuing the t w i slave response command cmd=0b11, it takes 1 peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 27. wdr instruction inside closed window will not issue reset w hen a w dr instruction is execute within one ulp clock cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround w ait at least one ulp clock cycle before executing a w dr instruction. 36.2.3 rev. a not sampled.
124 8068t?avr?12/10 xmega a3 37. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 37.1 8068t ? 12/10 37.2 8068s ? 09/10 37.3 8068r ? 08/10 1. datasheet status changed to complete: preliminary removed from the front page. 2. updated all tables in the ?electrical characteristics? . 3. updated ?packaging information? on page 61 . 4. replaced table 34-11 on page 69 5. replaced table 34-18 on page 71 and added the figure ?tosc input capacitance? on page 71 6. added errata ?rev. e? . 7. added errata ?rev. b? . 8. updated errata for adc (adc has increased inl error for some operating conditions). 9. updated the last page by atmel new brand style guide. 10. updated ?errata? on page 93 . 1. updated the footnote 3 of ?ordering information? on page 2 . 2. updated footnote 2 of figure 2-1 on page 3 . 3. updated ?data memory map (hexadecimal address)? on page 11 . 192a3 has 2 kb eeprom. 4. updated ?features? on page 27 . event channel 0 output on port pin 7. 5. updated ?absolute maximum ratings*? on page 63 by adding icc for flash/eeprom programming. 6. added avcc in ?adc characteristics? on page 67 . 7. updated start up time in ?adc characteristics? on page 67 . 8. updated ?dac characteristics? on page 68 . removed dc output impedence. 9. updated figure 35-6 on page 74 . replaced the figure by a correct one. 10. fixed typo in ?errata? section.
125 8068t?avr?12/10 xmega a3 37.4 8068q ? 02/10 37.5 8068p ? 02/10 37.6 8068o ? 11/09 37.7 8068n ? 10/09 37.8 8068m ? 09/09 1. added ?pdi speed? on page 92 . 1. updated the device pin-out figure 2-1 on page 3 . pdi_clk and pdi_data renamed only pdi. 2. removed jtag reset from the datasheet. 3. updated ?dac - 12-bit digital to analog converter? on page 43 . dac uses internal 1.0 voltage. 4. added table 34-19 on page 71 . 5. updated ?timer/counter and a w ex functions? on page 49 . 6. updated ?alternate pin function description? on page 49 . 7. updated all ?electrical characteristics? on page 63 . 8. updated ?pad characteristics? on page 69 . 9. changed internal oscillator speed to ?oscillators and w ake-up time? on page 88 . 10. updated ?errata? on page 93 1. updated table 34-3 on page 66 , endurance and data retention. 2. updated table 34-11 on page 69 , input hysteresis is in v and not in mv. 3. updated ?errata? on page 93 . 1. updated ?errata? on page 93 . 1. updated ?electrical characteristics? on page 63 . 2. added ?flash and eeprom memory characteristics? on page 66 . 3. added errata for ?atxmega192a3, ATXMEGA128A3, atxmega64a3? on page 110 .
126 8068t?avr?12/10 xmega a3 37.9 8068l ? 06/09 37.10 8068k ? 02/09 37.11 8068j ? 12/08 37.12 8068i ? 11/08 37.13 8068h ? 10/08 37.14 8068g ? 09/08 1. updated ?ordering information? on page 2 . 2. updated ?features? on page 39 . 3. updated ?overview? on page 43 . 4. updated ?overview? on page 48 . 5. added ?electrical characteri stics? on page 63 . 6. added ?typical characteristics? on page 72 . 7. updated ? ?errata? on page 93 . 1. added ?errata? on page 93 for atxmega256a3 rev b. 1. added ?errata? on page 93 for atxmega256a3 rev a. 1. updated featurelist in ?memories? on page 9 . 1. updated table 14-1 on page 25 . 1. updated ?features? on page 1 . 2. updated ?ordering information? on page 2 . 3. updated ?features? on page 9 by removing ?external memory...?. 4. updated figure 7-1 on page 10 and figure 7-2 on page 11 .
127 8068t?avr?12/10 xmega a3 37.15 8068f ? 08/08 37.16 8068e ? 08/08 37.17 8068d ? 06/08 37.18 8068c ? 06/08 37.19 8068b ? 06/08 5. updated table 7-2 on page 14 and table 7-3 on page 14 . 6. updated ?features? on page 41 and ?overview? on page 41 . 7 removed ?interrupt vector summary? section from datasheet. 1. changed figure 2-1 ?s title to ?block diagram and pinout.? 2. changed package type to ?64m2? in ?ordering information? on page 2 and in ?errata? on page 93 . 3. updated table 30-5 on page 52 . 4. inserted a correct ?64a? tqfp drawing on page 61 . 1. updated ?block diagram? on page 5 . 2. inserted ?interrupt vector summary? on page 54 . 1. references to external bus interface (ebi) removed from ?features? on page 1 . 1. updated ?features? on page 1 . 2. updated figure 2-1 on page 3 . 3. updated ?overview? on page 4 . 4. updated table 7-2 on page 14 . 5. replaced figure 25-1 on page 42 by a correct one. 6. updated ?features? and ?overview? on page 43 . 7. updated all tables in section ?alternate pin functions? on page 51 . 1. updated ?features? on page 1 . 2. updated ?? on page 2 and ?pinout and pin functions? on page 49 . 3. updated ?ordering information? on page 2 .
128 8068t?avr?12/10 xmega a3 37.20 8068a ? 02/08 4. updated ?overview? on page 4 , included the xmega a3 explanation text on page 6. 5. added xmega a3 block diagram, figure 3-1 on page 5 . 6. updated avr cpu ?overview? on page 7 and updated figure 6-1 on page 7 . 7. updated event system block diagram, figure 9-1 on page 17 . 8. updated ?pmic - programmable multi-level interrupt controller? on page 25 . 9. updated ?ac - analog comparator? on page 44 . 10. updated ?i/o configuration? on page 27 . 11. inserted a new figure 16-1 on page 32 . 12. updated ?peripheral module address map? on page 56 . 13. inserted ?instruction set summary? on page 57 . 14. added speed grades in ?operating voltage and frequency? on page 65 . 1. initial revision.
i 8068t?avr?12/10 xmega a3 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 typical applications .............. .............. .............. .............. .............. .......... 1 1 ordering information .......... .............. ............... .............. .............. ............ 2 2 pinout/block diagram ......... .............. ............... .............. .............. ............ 3 3 overview ............ ................ ................ ............... .............. .............. ............ 4 3.1block diagram ...........................................................................................................5 4 resources .............. .............. .............. ............... .............. .............. ............ 6 4.1recommended reading .............................................................................................6 5 disclaimer .............. .............. .............. ............... .............. .............. ............ 6 6 avr cpu ............ ................ ................ ............... .............. .............. ............ 7 6.1features ................................................................................................................... .7 6.2overview ................................................................................................................... 7 6.3register file .............................................................................................................. 8 6.4alu - arithmetic logic unit .......................................................................................8 6.5program flow ............................................................................................................8 7 memories ............... .............. .............. ............... .............. .............. ............ 9 7.1features ................................................................................................................... .9 7.2overview ................................................................................................................... 9 7.3in-system programmable flash program memory .................................................10 7.4data memory ...........................................................................................................11 7.5production signature row .......................................................................................13 7.6user signature row ................................................................................................13 7.7flash and eeprom page size ...............................................................................14 8 dmac - direct memory access controller ............... ................. .......... 15 8.1features ..................................................................................................................1 5 8.2overview .................................................................................................................15 9 event system ........ .............. .............. ............... .............. .............. .......... 16 9.1features ..................................................................................................................1 6 9.2overview .................................................................................................................16 10 system clock and clock options ................ ................. .............. .......... 18 10.1features ................................................................................................................18
ii 8068t?avr?12/10 xmega a3 10.2overview ...............................................................................................................18 10.3clock options ........................................................................................................19 11 power management and sleep modes ........ ................. .............. .......... 21 11.1features ................................................................................................................21 11.2overview ...............................................................................................................21 11.3sleep modes .........................................................................................................21 12 system control and reset .... .............. .............. .............. .............. ........ 23 12.1features ................................................................................................................23 12.2resetting the avr .................................................................................................23 12.3reset sources .......................................................................................................23 13 wdt - watchdog timer ......... .............. .............. .............. .............. ........ 24 13.1features ................................................................................................................24 13.2overview ...............................................................................................................24 14 pmic - programmable multi-l evel interrupt controller ............. .......... 25 14.1features ................................................................................................................25 14.2overview ...............................................................................................................25 14.3interrupt vectors ....................................................................................................25 15 i/o ports ............... ................ .............. ............... .............. .............. .......... 27 15.1features ................................................................................................................27 15.2overview ...............................................................................................................27 15.3i/o configuration ....................................................................................................27 15.4input sensing .........................................................................................................30 15.5port interrupt .........................................................................................................30 15.6alternate port functions ........................................................................................30 16 t/c - 16-bits timer/counter with pwm ........... .............. .............. .......... 31 16.1features ................................................................................................................31 16.2overview ...............................................................................................................31 17 awex - advanced waveform extension .... ................. .............. .......... 33 17.1features ................................................................................................................33 17.2overview ...............................................................................................................33 18 hi-res - high resolution extension .......... ................ ................. .......... 34 18.1features ................................................................................................................34 18.2overview ...............................................................................................................34
iii 8068t?avr?12/10 xmega a3 19 rtc - real-time counter ... .............. ............... .............. .............. .......... 35 19.1features ................................................................................................................35 19.2overview ...............................................................................................................35 20 twi - two wire interface .... .............. ............... .............. .............. .......... 36 20.1features ................................................................................................................36 20.2overview ...............................................................................................................36 21 spi - serial peripher al interface ............ .............. .............. ............ ........ 37 21.1features ................................................................................................................37 21.2overview ...............................................................................................................37 22 usart ............. ................. ................ ................. .............. .............. .......... 38 22.1features ................................................................................................................38 22.2overview ...............................................................................................................38 23 ircom - ir communication module .............. .............. .............. .......... 39 23.1features ................................................................................................................39 23.2overview ...............................................................................................................39 24 crypto engine ............ ................ ................. ................ ................. .......... 40 24.1features ................................................................................................................40 24.2overview ...............................................................................................................40 25 adc - 12-bit analog to digi tal converter ....... .............. .............. .......... 41 25.1features ................................................................................................................41 25.2overview ...............................................................................................................41 26 dac - 12-bit digital to an alog converter ................ ................ ............. 43 26.1features ................................................................................................................43 26.2overview ...............................................................................................................43 27 ac - analog comparator .... .............. ............... .............. .............. .......... 44 27.1features ................................................................................................................44 27.2overview ...............................................................................................................44 27.3input selection .......................................................................................................46 27.4 w indow function ...................................................................................................46 28 ocd - on-chip debug ......... .............. ............... .............. .............. .......... 47 28.1features ................................................................................................................47 28.2overview ...............................................................................................................47 29 program and debug interfaces .... ................ ................. .............. .......... 48
iv 8068t?avr?12/10 xmega a3 29.1features ................................................................................................................48 29.2overview ...............................................................................................................48 29.3ieee 1149.1 (jtag) boundary-scan ....................................................................48 30 pinout and pin functions ................. ............... .............. .............. .......... 49 30.1alternate pin function description ........................................................................49 30.2alternate pin functions .........................................................................................51 31 peripheral module addr ess map ............... ................ ................. .......... 56 32 instruction set summary ... .............. ............... .............. .............. .......... 57 33 packaging information .......... .............. .............. .............. .............. ........ 61 33.164a ....................................................................................................................... .61 33.264m2 .....................................................................................................................6 2 34 electrical characteristics ... .............. ............... .............. .............. .......... 63 34.1absolute maximum ratings* .................................................................................63 34.2dc characteristics ................................................................................................63 34.3operating voltage and frequency ........................................................................65 34.4flash and eeprom memory characterist ics ................ ................ ............. ..........66 34.5adc characteristics ..............................................................................................67 34.6dac characteristics ..............................................................................................68 34.7analog comparator characteristics .......................................................................68 34.8bandgap characteristics .......................................................................................68 34.9brownout detection characteristics ......................................................................69 34.10pad characteristics ............................................................................................69 34.11por characteristics ............................................................................................70 34.12reset characteristics ..........................................................................................70 34.13oscillator characteristics .....................................................................................70 35 typical characteristics ....... .............. ............... .............. .............. .......... 72 35.1active supply current ............................................................................................72 35.2idle supply current ................................................................................................75 35.3power-down supply current .................................................................................79 35.4power-save supply current ..................................................................................80 35.5pin pull-up .............................................................................................................80 35.6pin output voltage vs. sink/source current .........................................................82 35.7pin thresholds and hysteresis ..............................................................................85 35.8bod thresholds .....................................................................................................87
35.9oscillators and w ake-up time ..............................................................................88 35.10module current consumption ...............................................................................91 35.11reset pulsewidth .................................................................................................92 35.12pdi speed ...........................................................................................................92 36 errata ............. ................ ................. ................ ................. .............. .......... 93 36.1atxmega256a3 .....................................................................................................93 36.2atxmega192a3, ATXMEGA128A3, atxmega64a3 .............................................110 37 datasheet revision history .. ................ ................. ................ ............. 124 37.18068t ? 12/10 .....................................................................................................124 37.28068s ? 09/10 .....................................................................................................124 37.38068r ? 08/10 .....................................................................................................124 37.48068q ? 02/10 .....................................................................................................125 37.58068p ? 02/10 .....................................................................................................125 37.68068o ? 11/09 .....................................................................................................125 37.78068n ? 10/09 .....................................................................................................125 37.88068m ? 09/09 ....................................................................................................125 37.98068l ? 06/09 .....................................................................................................126 37.108068k ? 02/09 ...................................................................................................126 37.118068j ? 12/08 ....................................................................................................126 37.128068i ? 11/08 ....................................................................................................126 37.138068h ? 10/08 ...................................................................................................126 37.148068g ? 09/08 ...................................................................................................126 37.158068f ? 08/08 ...................................................................................................127 37.168068e ? 08/08 ...................................................................................................127 37.178068d ? 06/08 ...................................................................................................127 37.188068c ? 06/08 ...................................................................................................127 37.198068b ? 06/08 ...................................................................................................127 37.208068a ? 02/08 ...................................................................................................128 table of contents.......... ................. ................ ................. ................ ........... i
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